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RAM Implementation (standard cells method)

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Lance850210

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Hi people,

May I know how can I implement RAMs using semicustom method? I am implementing a digital application which requires RAMs. How can I implement a RAM without customly design the cells, sensing amplifier, decoders, etc.? I am using standard cells from STM65nm technology library to synthesize the Verilog code of other blocks in the application. Can I also synthesize RAMs in the same way as the other blocks do? If yes, how should I code the module so that the synthesis outcome is RAM?

Thanks in advance.

Cheers!
 

Sounds like you're doing ASIC. Ask the vendor that supplied the libraries for documentation.
 

Hi,

as brownout mentioned the vendor should have a RAM library or a RAM compiler to generate different RAM types.

If you want to synthesize a RAM you need to code a register bank
(this normally takes more area)

I once coded a dual port (one write port and one read port) ram like this

Code: 
module rw_ram ( A   ,
                        I   ,
                        IW  ,
                        RA  ,
                        CKIW,
                        CKRA,
                        CEIW,
                        CERA ) ;
  
  parameter  DATA_WIDTH = 44,
             ADDRESS_WIDTH = 2 ;
  
  input wire CKIW, CKRA ;//clocks
  input wire CEIW, CERA ;//enables
  input wire [DATA_WIDTH - 1:0] I ;//data in
  input wire [ADDRESS_WIDTH - 1:0] IW, RA ;//addresses
  
  output reg [DATA_WIDTH - 1:0] A ;//read data
  
  reg [2**ADDRESS_WIDTH*DATA_WIDTH - 1:0] mem;
  
  always @(posedge CKIW)
    if ( ~CEIW )
      mem[IW*DATA_WIDTH +: DATA_WIDTH] <= I ;
  
  always @(posedge CKRA)
    if ( ~CERA )
      A <= mem[RA*DATA_WIDTH +: DATA_WIDTH] ;

  
endmodule
 

Hi Brownout and Qieda,

Thank you so much. =D
 

Hi Lance850210,

Could you share your verilog code example?
Thanks.
 

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