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Hold Violation in Tester and regeneration of ATPG with hold mask

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dbshailesh

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ASIC-DFT Hold Violation in Tester and regeneration of ATPG with hold mask

Hi ,
Can any body discuss about the procedures to generate the patterns, for silicon-hold violation issue -seen on a chain/flop.

In Brief:
On silicon I am seeing a hold violation on a chain and have identified the flop, now can we re-generate the patterns with hold flop mask or (Any other procedure) ?
Explain, different methods of pattern regeneraion or to address the already present hold issue in silicon
 
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For the chain with issues, ignore the scanout data from the certain point(you said you identified the flop with hold viol).
For the chains other than the one with issues, ignore all the flops that are within a logic cone starting at the flop with hold viols and beyond in the troubled chain.
 
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lostinxlation said:
For the chain with issues, ignore the scanout data from the certain point(you said you identified the flop with hold viol).
For the chains other than the one with issues, ignore all the flops that are within a logic cone starting at the flop with hold viols and beyond in the troubled chain.
Click to expand...

Thanks , but Could you please elaborate your answer, the take cares to be done in shift and capture procedure....
 

I think that a hold violation would cause the flip-flop with the hold violation to disappear. Your scan chain would operate as if that flip-flop did not exists because it and the flip-flop that feeds it will capture the same value as you shift the scan chain.
 

:?: :-x
What is the solution? Please recheck the question once again.
This is a discussion topic. We can discuss all the available solutions for hold-issue on silicon.
 

Whatever passing through the ff with hold viols while shifting cannot be trusted. Plain and simple. What more do you want to know ?
 

lostinxlation,
Exactly you are correct for the violation falling in hold window,
I am also expecting for the other scenario
i.e. if the hold value changes before the setup, so no metastability is present.

__ | __
__| |__| |__
 

Create a pattern with alternating 0s and 1s. The shift it in and out of our chip and remove effects of scan inversions. Then analyze bits near flip-flop with hold violation. Is it always the same as the value scanned into the flip-flop that feeds it in the chain? Then the effect is that you have 1 less flip-flop in the chain.

You could also analyze the timing reports where you have the failure. Determine if the value captured by the flip-flop is unknown or the same value loaded into the feeding flip-flop in the chain.
 

ConradATPG said:
Create a pattern with alternating 0s and 1s. The shift it in and out of our chip and remove effects of scan inversions. Then analyze bits near flip-flop with hold violation. Is it always the same as the value scanned into the flip-flop that feeds it in the chain? Then the effect is that you have 1 less flip-flop in the chain.

You could also analyze the timing reports where you have the failure. Determine if the value captured by the flip-flop is unknown or the same value loaded into the feeding flip-flop in the chain.
Click to expand...

Ok.. let me repeat....
Issue is present on Silicon and I have identified the flop with hold violation (not a metastability), so the expected data is coming one cycle ahead..
Then what would be the solution w.r.t. atpg.
 

dbshailesh said:
Ok.. let me repeat....
Issue is present on Silicon and I have identified the flop with hold violation (not a metastability), so the expected data is coming one cycle ahead..
Then what would be the solution w.r.t. atpg.
Click to expand...
Why do you think all the data comes oen cycle ahead ? You have a big mistake in understanding here since unless you TOTALLY screw up the timing analysis, hold viols in silicon is very subtle and it may violate or may not violate depending on many factors like IR drop and process corner and such.

Like I said, it's very simple. You cannot trust any data throught he failing flop. THat's all and nothing else. You have to set the tool to ignore those data potetially corrupted. There is no solution other than that.
 

lostinxlation said:
Why do you think all the data comes oen cycle ahead ? You have a big mistake in understanding here since unless you TOTALLY screw up the timing analysis, hold viols in silicon is very subtle and it may violate or may not violate depending on many factors like IR drop and process corner and such.

Like I said, it's very simple. You cannot trust any data throught he failing flop. THat's all and nothing else. You have to set the tool to ignore those data potetially corrupted. There is no solution other than that.
Click to expand...

Hi,
Let me answer, By modifying the netlist for failing flop we can re-generate the patterns and validate the silicon , this is one method.
So like this I wanted to know is their any other method/soltions present to test the silicon.
 

dbshailesh said:
Hi,
Let me answer, By modifying the netlist for failing flop we can re-generate the patterns and validate the silicon , this is one method.
So like this I wanted to know is their any other method/soltions present to test the silicon.
Click to expand...
How does modifying netlist help ? You still need to mask some registers.
 
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If there are no meta-stability issues and the hold violation is on the scan path only then:

1) There are 3 flip-flops that are effected by this problem. They are HVFF, HVFF-1, and HVFF-2 where HVFF has the hold violation, HVFF-1 feeds HVFF and HVDD-2 feeds HVFF-1.

2) HVFF's scan input should be driven by HVFF-2.

3) HVFF-1's scan input should be driven by HVFF-2, and have it's D input masked.
 

lostinxlation said:
How does modifying netlist help ? You still need to mask some registers.
Click to expand...

Actually a hold causes the data shift out a cycle faster, so expected data comes a cycle early, so bypass the hold-violated flop from the chain, by hacking the netlist and regenerate the patterns also you have to mask the capture data coming to the hold-violating flop.
Here we definitely loose some coverage.

8)

Regards,
Shailesh
 

Like I said, it's not realistic. Have you ever seen the hold violation on the silison ? It's not always violating the hold viols since the timing analysis was done and closed before the tapeout. When hold viols happen on the silicon, it's very subtle affected by the IR drop, process corners, and so on that went beyond the assumption in the pre-tapeout analysis. When the hold viols may or may not happen, assuming hold violation happens all the time would backfire since the perfectly good chips get errors and discarded. Like I said, masking all the affected flops is the only realistic solution to give you a solild result.

If you have a hold viol on a flop which happens to an extent that it always violate, the hold viols must be quite great and the timng analysis was done totally wrong. With such a lousy timing analysis, I can assure you that there are so many more flops grossly violating the hold time and you won't be able to handle the test in a way you described.
 
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lostinxlation said:
If you have a hold viol on a flop which happens to an extent that it always violate, the hold viols must be quite great and the timng analysis was done totally wrong. With such a lousy timing analysis, I can assure you that there are so many more flops grossly violating the hold time and you won't be able to handle the test in a way you described.
Click to expand...

It could be that they forgot to do timing analysis on the scan path.
 

Re: ASIC-DFT Hold Violation in Tester and regeneration of ATPG with hold mask

How to identify the failing flop during chain test failure on silicon ?
 

Tessent family tool has tool which could read a failure report from ATE, and will indicate what is the source of the falling patters.

Or as you know the number cycle which fails, you could know which flop has the wrong value.
 

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