+ Post New Thread
Results 1 to 2 of 2
  1. #1
    Newbie level 1
    Points: 371, Level: 4

    Join Date
    Dec 2010
    Posts
    1
    Helped
    0 / 0
    Points
    371
    Level
    4

    Verilog: displaying Real number during simulation

    i'm currently doing a simulation debug involving calculations. The real numbers i'm interested to observe involve some maths regarding $realtime. I believe something's wrong in the behavioral model of the PLL when it's calculating the period of the refclk/fbclk etc...

    Unfortunately, the data stored as "real" cannot be pulled out as sim waveforms. Is there a workaround? Is it possible to store the real numbers into "reg", and then display the waveform? Pls advice...many thanks.

    •   AltAdvertisment

        
       

  2. #2
    Full Member level 5
    Points: 4,114, Level: 15
    Achievements:
    7 years registered
    RBB's Avatar
    Join Date
    Jul 2007
    Location
    USA
    Posts
    304
    Helped
    70 / 70
    Points
    4,114
    Level
    15

    Re: Verilog: displaying Real number during simulation

    Why can't you probe real signals in your waveform viewer? Which simulator are you using?



--[[ ]]--