Single-Port RAM with Asynchonous Read: RAM A overlap RAM B

entity TryCode is
    Port ( clk : in  STD_LOGIC;
           addra : in  STD_LOGIC_VECTOR (7 downto 0);
           dina : in  STD_LOGIC_VECTOR (15 downto 0);
           writea : in  STD_LOGIC;
           addrb : in  STD_LOGIC_VECTOR (7 downto 0);
           dinb : in  STD_LOGIC_VECTOR (15 downto 0);
           writeb : in  STD_LOGIC;
           readab : in  STD_LOGIC;
           regenable : in  STD_LOGIC;
			   doout1: inout std_logic_vector(15 downto 0);
				doout2: inout std_logic_vector(15 downto 0);	
			  dout : out std_logic_vector (15 downto 0));
			  		
end TryCode;

architecture Structural of TryCode is
component RAM
port ( clk: in std_logic;
we: in std_logic;
a: in std_logic_vector(7 downto 0);
di: in std_logic_vector(15 downto 0);
do: out std_logic_vector(15 downto 0));
end component;
component dec
port ( din: in std_logic;
reset: in std_logic;
outp1 : out std_logic;
outp2 : out std_logic);
end component;
component Three_st
port( T: in std_logic;
I: in std_logic_vector(15 downto 0);
O: out std_logic_vector(15 downto 0));
end component;
component register16
port ( C,enable:in std_logic;
D: in std_logic_vector(15 downto 0);
Q: out std_logic_vector(15 downto 0));
end component;
component adder16
port (A,B: in std_logic_vector(15 downto 0);
SUM: out std_logic_vector(15 downto 0));
end component;
--signal doout1: std_logic_vector(15 downto 0);
--signal doout2: std_logic_vector(15 downto 0);
signal res: std_logic;
signal OE1: std_logic;
signal OE2: std_logic;
signal regout: std_logic_vector(15 downto 0);
signal busout: std_logic_vector (15 downto 0);
begin

RAM_A: RAM port map(clk => clk, we => writea, a => addra, di => dina, do => doout1);
RAM_B: RAM port map(clk => clk, we => writeb, a => addrb, di => dinb, do => doout2);
decoder1: dec port map (din => readab, reset => res, outp1 => OE1, outp2 => OE2);
gate: nor2 port map(I0 => writea, I1 => writeb, O => res);
buf1: Three_st port map (I => doout1, T => OE1, O => busout);
buf2: Three_st port map (I => doout2, T => OE2, O => busout);
reg: register16 port map (C => clk, enable => regenable, D => busout, Q => regout);
sumator: adder16 port map (A => regout, B => busout, SUM => dout);




end Structural;

entity RAM is
port ( clka: in std_logic;
wea: in std_logic;
a: in std_logic_vector(7 downto 0);
dia: in std_logic_vector(15 downto 0);
doa: out std_logic_vector(15 downto 0);
clkb: in std_logic;
web: in std_logic;
b: in std_logic_vector(7 downto 0);
dib: in std_logic_vector(15 downto 0);
dob: out std_logic_vector(15 downto 0));


end RAM;

architecture Behav4 of RAM is
type ram_type is array (255 downto 0) of std_logic_vector(15 downto 0);

shared variable ram : ram_type;
begin
process(clka)
begin
if CLKA'event and CLKA = '1' then
                if WEA = '1' then
                    RAM(conv_integer(a)) := DIA;
                end if;
                	DOA <= RAM(conv_integer(a)); 		
            end if;
    end process;
	 
	 process (CLKB)
    begin
        if CLKB'event and CLKB = '1' then
        
                if WEB = '1' then
                    RAM(conv_integer(b)) := DIB;
                end if;
           		DOB <= RAM(conv_integer(B));

 	
    end if;
	 
    end process;

end Behav4;