How to synthesis a GTETCH netlist？？

hello every one！
I have a gtech netlist and need to implement it on FPGA and on AISC Design. But now I'm not sure about the way I deal with it.
The way I choose is as follows :
Bcz the UDPs are not synthesisable, So I redescript all the UDPs in a synthesisable format. for example :
the original format of a UDP like this :
primitive GTECH_UDP_FD1 (Q, D, CP);
output Q;
input D, CP;
reg Q;

// FUNCTION : DFF

table
// D CP : Q : Qt+1
//-------------------------
0 (01) : ? : 0;
1 (01) : ? : 1;
0 (0x) : 0 : 0;
0 (x1) : 0 : 0;
1 (0x) : 1 : 1;
1 (x1) : 1 : 1;
? (?0) : ? : -;
? (1x) : ? : -;
* ? : ? : -;

endtable
endprimitive

after redescription like this :


module GTECH_UDP_FD1 (Q, D, CP);
output Q;
input D, CP;
reg Q;

always @(posedge CP)

Q <= D;
endmodule

I wonder if there is any other better way to implement a gtech netlist on FPGA or ASIC(Design Compiler)?

Hi,

If your netlist is in GTECH format shouldn't you be able to read it into design_compiler and remap it to the target technology?