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  1. #1
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    Verilog code of 8 bit register with load facility

    anyone have code of 8 bit register with load facility ,

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  2. #2
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    Re: verilog program code

    do you mean something like this:

    reg [7:0] my_reg;
    wire [7:0] new_data;
    wire load_my_reg;
    always @( posedge clk )
    if(load_my_reg)
    my_reg <= new_data;

    (you'll need to assign something to the new_data bus and the load_my_reg signal, and to take care of the clk)



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