Help! My error: Found logic contention at 40ns on node 'D0'

logic contention

I am a green hand to VHDL. Now I design a ASIC to realize the full funcions of MITSUBISHI M66500 SP/FP PROGRAMMABLE BUFFERED I/O EXPANDER.
But I encounter some differences, especially the "InOut" Port. I minimize my code to represent the main function below.
Can you give some advices about the code?

MAX+Plus II 10.23 Full. The Compiling is OK, but the simulation show such error message: Warning:Found logic contention at 40ns on node 'D0'
Warning:Found logic contention at 40ns on node 'D1'
...
Warning:Found logic contention at 40ns on node 'A7'

Beg your help!

--*************************************
Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Arith.All;
Use IEEE.Std_Logic_Unsigned.All;
--*************************************
Entity M66500 Is
Port(
Address: In Std_Logic_Vector(2 Downto 0);
D: InOut Std_Logic_Vector(7 Downto 0);
RST: In Std_Logic;
CS: In Std_Logic;
WR: In Std_Logic;
RD: In Std_Logic;
A: InOut Std_Logic_Vector(7 Downto 0)

);
End M66500;
--*************************************
Architecture a Of M66500 Is
Signal Status: Std_Logic_Vector(7 Downto 0) := "11111111";
Signal BitCon: Std_Logic_Vector(7 Downto 0) := "00000000";
Signal BuffA: Std_Logic_Vector(7 Downto 0);

Begin

Process(Address, CS, RD, WR, RST)
Variable Sel: Std_Logic_Vector(3 Downto 0);
Begin
Sel := CS & Address;
If RST = '1' And CS = '0' Then
Status <= "11111111";
ElsIf WR'Event And WR = '1' Then --Write D to Ports
Case Sel Is
When "0000" => --Write D to A if permit, or to BuffA if not
BuffA <= D;
If Status(3) = '0' Then
A <= BuffA;
Elsif Status(3) = '1' Then
A <= "ZZZZZZZZ";
End If;
When "0111" => --Write order to Control Register
If D(7) = '0' Then
BitCon <= D;
ElsIf D(7) = '1' Then
Status <= D;
End If;
When Others =>
Null;
End Case;
End If;

If RD = '0' Then --Read A to Port D
Case Sel Is
When "0000" => --Read From A to D If permit, or from BuffA if not
If Status(3) = '1' Then
D <= A;
Elsif Status(3) = '0' Then
D <= BuffA;
End If;
When Others =>
Null;
End Case;
End If;


End Process;

End a;

found logic contention

What it happens in your simulation at 40 ns? maybe the reset release?

in your code branch, D and A outputs are'nt set to high impedance state: this could lead to a bus contention with your A and D testbench inputs!

An inout port cannot be driven from two signals at the same time: one (or both) must be set to "Z"... maybe this could be the problem?

warning: found logic contention at time

Thank you for your reply. But I have set "ZZZZZZZZ", why not functional?

In this project, there are 2 control register - "Status" and "BitCon". The functions of port, input or output, is determined by Status.

When data put out port A, data will be put into BuffA, if Port A has been set as output before, the data will be put out through A directly. Or if Port A has been as input before, the data will be put into BuffA only.

When read from Port A, if Port A has been set as output before, data will be read from BuffA only, otherwise from Port A.

What can I do? :?:

found logic contention at time on bus node

rol73 said:

What it happens in your simulation at 40 ns? maybe the reset release?

in your code branch, D and A outputs are'nt set to high impedance state: this could lead to a bus contention with your A and D testbench inputs!

An inout port cannot be driven from two signals at the same time: one (or both) must be set to "Z"... maybe this could be the problem?

Click to expand...

At 40ns, there is nothing but a WR rise up edge.
Thank you!

lm016l logic contention

your codes have some problems you shouldn't assign constant variable to
your signal status and bitcon that your processs always do elsif
Signal Status: Std_Logic_Vector(7 Downto 0) = "11111111";
If Status(3) = '0' Then
A <= BuffA;
Elsif Status(3) = '1' Then
A <= "ZZZZZZZZ";
other problem you should notice the diffrence
between cs&address and address&cs
cs&address=>sel(4)=cs sel(0)=address(0)
adress&cs =>sel(4)= address(2) sel(0)=cs
i think you should replace address&cs

proteus logic contention

mc&fpga said:

your codes have some problems you shouldn't assign constant variable to
your signal status and bitcon that your processs always do elsif
Signal Status: Std_Logic_Vector(7 Downto 0) = "11111111";
If Status(3) = '0' Then
A <= BuffA;
Elsif Status(3) = '1' Then
A <= "ZZZZZZZZ";
other problem you should notice the diffrence
between cs&address and address&cs
cs&address=>sel(4)=cs sel(0)=address(0)
adress&cs =>sel(4)= address(2) sel(0)=cs
i think you should replace address&cs

Click to expand...

I followed your advices and reedit my code (except "cs & address", I think it right). but the result is the same as before. It is the simulation result below.
:?:
--*************************************
Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Arith.All;
Use IEEE.Std_Logic_Unsigned.All;
--*************************************
Entity M66500 Is
Port(
Address: In Std_Logic_Vector(2 Downto 0);
D: InOut Std_Logic_Vector(7 Downto 0);
RST: In Std_Logic;
CS: In Std_Logic;
WR: In Std_Logic;
RD: In Std_Logic;
A: InOut Std_Logic_Vector(7 Downto 0)

);
End M66500;
--*************************************
Architecture a Of M66500 Is
Signal Status: Std_Logic_Vector(7 Downto 0);
Signal BitCon: Std_Logic_Vector(7 Downto 0);
Signal BuffA: Std_Logic_Vector(7 Downto 0);

Begin

Process(Address, CS, RD, WR, RST)
Variable Sel: Std_Logic_Vector(3 Downto 0);
Begin
Sel := CS & Address;
If RST = '1' And CS = '0' Then
Status <= "11111111";
ElsIf WR'Event And WR = '1' Then --Write D to Ports
Case Sel Is
When "0000" => --Write D to A if permit, or to BuffA if not
BuffA <= D;
If Status(3) = '0' Then
A <= BuffA;
Elsif Status(3) = '1' Then
A <= "ZZZZZZZZ";
End If;
When "0111" => --Write order to Control Register
If D(7) = '0' Then
BitCon <= D;
ElsIf D(7) = '1' Then
Status <= D;
End If;
When Others =>
Null;
End Case;
End If;

If RD = '0' Then --Read from A to D
Case Sel Is
When "0000" => --Read From A to D If permit, or from BuffA if not
If Status(3) = '1' Then
D <= A;
Elsif Status(3) = '0' Then
D <= BuffA;
End If;
When Others =>
Null;
End Case;
End If;


End Process;

End a;

8051 logic contention

at 40ns your process is active thanks the sensitivity list for changing. d in (ff) will conflict d out(BufA).
although, the read part of the process does null, this only means d out keeps the previous state: BufA. (i think it is not the only one event during the course of the simulation that causes conflict, if i am not fail.)
basically, i prefer control the bus in master-slave relation: one drives and one receives at a time.
To do this, try to infer 3state buffers and their control. It is almost always works.
anyway, your m66500 chip datasheet is available?

found logic contention

Husoo said:

at 40ns your process is active thanks the sensitivity list for changing. d in (ff) will conflict d out(BufA).
although, the read part of the process does null, this only means d out keeps the previous state: BufA. (i think it is not the only one event during the course of the simulation that causes conflict, if i am not fail.)
basically, i prefer control the bus in master-slave relation: one drives and one receives at a time.
To do this, try to infer 3state buffers and their control. It is almost always works.
anyway, your m66500 chip datasheet is available?

Click to expand...

What you said is right. But I don't know how to use a state buffers in this project.
In this project "Status" is a control register to set the ports to input or output. "BitCon" is a control register to set the bit of Port C to 1 or 0.
I have a datasheet, but I am sorry it made in Japanese. M66500 has not been produced, so I am ask to 'copy' its functions to a CPLD (Altera EPM7128AE).
Thank you!
This is my all source and datasheet.

--*************************************
Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Arith.All;
Use IEEE.Std_Logic_Unsigned.All;
--*************************************
Entity M66500 Is
Port(
Address: In Std_Logic_Vector(2 Downto 0);
D: InOut Std_Logic_Vector(7 Downto 0);
RST: In Std_Logic;
CS: In Std_Logic;
WR: In Std_Logic;
RD: In Std_Logic;
A: InOut Std_Logic_Vector(7 Downto 0);
B: InOut Std_Logic_Vector(7 Downto 0);
C: InOut Std_Logic_Vector(7 Downto 0);
E: Out Std_Logic_Vector(7 Downto 0);
F: Out Std_Logic_Vector(7 Downto 0);
G: In Std_Logic_Vector(3 Downto 0)
);
End M66500;
--*************************************
Architecture a Of M66500 Is
Signal Status: Std_Logic_Vector(7 Downto 0) := "11111111"; --Control Register
Signal BitCon: Std_Logic_Vector(7 Downto 0) := "00000000"; --Set bit of Port C
Signal BuffA: Std_Logic_Vector(7 Downto 0); --Backup of Output of Port A
Signal BuffB: Std_Logic_Vector(7 Downto 0);
Signal BuffC: Std_Logic_Vector(7 Downto 0);
Signal BuffE: Std_Logic_Vector(7 Downto 0);
Signal BuffF: Std_Logic_Vector(7 Downto 0);
Begin

Process(Address, CS, RD, WR, RST)
Variable Sel: Std_Logic_Vector(3 Downto 0);
Begin
Sel := CS & Address;
If RST = '1' And CS = '0' Then
Status <= "11111111";
ElsIf WR'Event And WR = '1' Then --Write D to Ports
Case Sel Is
When "0000" => --Write to A
BuffA <= D;
If Status(3) = '0' Then
A <= BuffA;
Elsif Status(3) = '1' Then
A <= "ZZZZZZZZ";
End If;
When "0001" => --Write to B
BuffB <= D;
If Status(2) = '0' Then
B <= BuffB;
Elsif Status(2) = '1' Then
B <= "ZZZZZZZZ";
End If;
When "0010" => --Write to C
BuffC <= D;
If Status(1 Downto 0) = "00" Then
C <= BuffC;
Elsif Status(1) = '0' And Status(0) = '1' Then
C(7 Downto 4) <= BuffC(7 Downto 4);
Elsif Status(1) = '1' And Status(0) = '0' Then
C(3 Downto 0) <= BuffC(3 Downto 0);
Else
C <= "ZZZZZZZZ";
End If;
When "0100" => --Write to E
BuffE <= D;
If Status(5) = '0' Then
E <= BuffE;
End If;
When "0101" => --Write to F
BuffF <= D;
If Status(4) = '0' Then
F <= BuffF;
End If;
When "0111" =>
If D(7) = '0' Then -- Set bit of Port C
BitCon <= D;
If BitCon(3 Downto 1) = "000" And Status(0) = '0' Then
BuffC(0) <= BitCon(0);
C(0) <= BuffC(0);
Elsif BitCon(3 Downto 1) = "001" And Status(0) = '0' Then
BuffC(1) <= BitCon(0);
C(1) <= BuffC(1);
Elsif BitCon(3 Downto 1) = "010" And Status(0) = '0' Then
BuffC(2) <= BitCon(0);
C(2) <= BuffC(2);
Elsif BitCon(3 Downto 1) = "011" And Status(0) = '0' Then
BuffC(3) <= BitCon(0);
C(3) <= BuffC(3);
Elsif BitCon(3 Downto 1) = "100" And Status(1) = '0' Then
BuffC(4) <= BitCon(0);
C(4) <= BuffC(4);
Elsif BitCon(3 Downto 1) = "101" And Status(1) = '0' Then
BuffC(5) <= BitCon(0);
C(5) <= BuffC(5);
Elsif BitCon(3 Downto 1) = "110" And Status(1) = '0' Then
BuffC(6) <= BitCon(0);
C(6) <= BuffC(6);
Elsif BitCon(3 Downto 1) = "111" And Status(1) = '0' Then
BuffC(7) <= BitCon(0);
C(7) <= BuffC(7);
End If;
ElsIf D(7) = '1' Then -- Set Control Register
Status <= D;
End If;
-- When "1---" =>
-- D <= "ZZZZZZZZ";
When Others =>
Null;
End Case;
End If;

If RD = '0' Then --Read Ports to D
Case Sel Is
When "0000" => --Read From A
If Status(3) = '1' Then
D <= A;
Elsif Status(3) = '0' Then
D <= BuffA;
End If;
When "0001" => --Read From B
If Status(3) = '1' Then
D <= B;
Elsif Status(3) = '0' Then
D <= BuffB;
End If;
When "0010" => --Read From C
If Status(1 Downto 0) = "11" Then
D <= C;
Elsif Status(1) = '1' And Status(0) = '0' Then
D <= C(7 Downto 4) & Buffc(3 Downto 0);
Elsif Status(1) = '0' And Status(0) = '1' Then
D <= BuffC(7 Downto 4) & c(3 Downto 0);
End If;
When "0011" => --Read From G
D(3 Downto 0) <= G;
-- When "1---" =>
-- D <= "ZZZZZZZZ";
When Others =>
Null;
End Case;
End If;


End Process;

End a;

find logic contention

in first line, modify your testbench; you cannot read and write in the same time on the D bus, as i see. No busmaster does it so and now, your bench should behave like an MCU or whatever, i suppose.

hope the code below could be applied for your cpld.

entity cpld is
port(
...
D : inout Std_Logic_Vector(n downto 0);
rd : in Std_Logic;
...
);
end cpld;

architecture cpld_arch of cpld is

Sel: Std_Logic_Vector(3 Downto 0);
-- signals for the internal registers
Din : Std_Logic_Vector(n downto 0);
Dout : Std_Logic_Vector(n downto 0);

begin
...
Sel <= CS & Address;
Din <= D;
D <= Dout when rd = '0' else (others => 'Z');

-- write process, update ports/registers
process(...)
...
... <= Din;
end process;

-- give value for Dout depending on Sel and Status
process(Sel, Status)
...
Dout <= ...;
end process;

end cpld_arch;

And try to avoid:
If Status(3) = '1' Then
D <= A;
Elsif Status(3) = '0' Then
D <= BuffA;
End If;

use instead of it:
If Status(3) = '1' Then D <= A; else D <= BuffA; End If;

Thats almost all there is to it.
Hope this helps.

logic contentions detected

Husoo said:

in first line, modify your testbench; you cannot read and write in the same time on the D bus, as i see. No busmaster does it so and now, your bench should behave like an MCU or whatever, i suppose.

hope the code below could be applied for your cpld.
......
quote]

Thank you!
I think your advice will work well. But in this project, Port A (and B, C, E, F, G) is bi-directional ports as well as Port D. According to your method, I should update the Port A when
Din <= D;
D <= Dout when rd = '0' else (others => 'Z');
as this:
Din <= D;
D <= Dout when rd = '0' else (others => 'Z');
Ain <= A;
A <= Aout when Status(3) = '0' else (others => 'Z');
??
And in the Process(sel, ...), I updat Din, Dout, Ain, Aout following the Status?
as
Case Sel Is
When "0000" =>
Aout <= Din;
Dout <= Ain;
...
End case;
??
What is most confused is that both A and D is bi-directional Port.

Click to expand...

warning: found logic contention at time

I rewrite my code, but "Found logic contention" warning exist too.
Here are two methods.

--*************************************
Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Arith.All;
Use IEEE.Std_Logic_Unsigned.All;
--*************************************
Entity M66500 Is
Port(
Address: In Std_Logic_Vector(2 Downto 0);
D: InOut Std_Logic_Vector(7 Downto 0);
S: InOut Std_Logic_Vector(7 Downto 0);
RST: In Std_Logic;
CS: In Std_Logic;
WR: In Std_Logic;
RD: In Std_Logic;
A: InOut Std_Logic_Vector(7 Downto 0)

);
End M66500;
--*************************************
Architecture a Of M66500 Is
Signal Status: Std_Logic_Vector(7 Downto 0);
Signal BitCon: Std_Logic_Vector(7 Downto 0);
Signal Din: Std_Logic_Vector(7 Downto 0);
Signal Dout: Std_Logic_Vector(7 Downto 0);
Signal Ain: Std_Logic_Vector(7 Downto 0);
Signal Aout: Std_Logic_Vector(7 Downto 0);
Signal Sel: Std_Logic_Vector(3 Downto 0);

Begin

Sel <= CS & Address;
Din <= D;
D <= Dout when RD = '0' else (others => 'Z');

Ain <= A;
A <= Aout when Status(3) = '0' and WR = '0' else (others => 'Z');

S <= Status; -- Test

Process(Sel,D,A,RST)
Begin

If RST = '1' And CS = '0' Then -- Reset the control register "Status"
Status <= "11111111";
End If;

Case Sel Is
When "0000" =>
Dout <= Ain;
Aout <= Din;
When "0111" =>
If Din(7) = '0' Then
BitCon <= Din;
ElsIf Din(7) = '1' Then
Status <= Din;
End If;
When Others =>
Null;
End Case;

End Process;

End a;

warning: found logic contention

--*************************************
Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Arith.All;
Use IEEE.Std_Logic_Unsigned.All;
--*************************************
Entity M66500 Is
Port(
Address: In Std_Logic_Vector(2 Downto 0);
D: InOut Std_Logic_Vector(7 Downto 0);
S: InOut Std_Logic_Vector(7 Downto 0);
RST: In Std_Logic;
CS: In Std_Logic;
WR: In Std_Logic;
RD: In Std_Logic;
A: InOut Std_Logic_Vector(7 Downto 0)

);
End M66500;
--*************************************
Architecture a Of M66500 Is
Signal Status: Std_Logic_Vector(7 Downto 0);
Signal BitCon: Std_Logic_Vector(7 Downto 0);
Signal Din: Std_Logic_Vector(7 Downto 0);
Signal Dout: Std_Logic_Vector(7 Downto 0);
Signal Sel: Std_Logic_Vector(3 Downto 0);

Begin

Sel <= CS & Address;
Din <= D;
D <= Dout when RD = '0' else (others => 'Z');

Process(Sel,WR,RD,RST)
Begin

If RST = '1' And CS = '0' Then -- Reset the control register "Status"
Status <= "11111111";
ElsIf WR'Event And WR = '1' Then --Write D to Ports

Case Sel Is
When "0000" => --Write D to A if permit, or to BuffA if not
BuffA <= Din;
If Status(3) = '0' Then
A <= BuffA;
Else
A <= "ZZZZZZZZ";
End If;

When "0111" => --Write order to Control Register
If Din(7) = '0' Then
BitCon <= Din;
ElsIf Din(7) = '1' Then
Status <= Din;
End If;
When Others =>
Null;
End Case;

End If;

End Process;

Process(Sel,Status)
Begin

If RD = '0' Then --Read from A to D

Case Sel Is
When "0000" => --Read From A to D If permit, or from BuffA if not
If Status(3) = '1' Then
Dout <= A;
Else
Dout <= BuffA;
End If;
When Others =>
Null;
End Case;

End If;

End Process;

End a;

found logic contention at time on bus node

Please read



Baseline Version of Max+Plus II 10.23 can not use bi-directional port?
Has my Max+Plus II some problem with license? Or other problem?

found logic contention at time bus node

i am not expert with max, but i am sure it is not license matter.
actually, what is your problem with bidir.vhd?

by, husoo

ps.: your e-mail address does not work...