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why to use assertions and what is their advandage?

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cyboman

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i had an interview question about this and i really couldn't answer. i would really appreciate if somebody could tell me.

the question is: why to use assertions in the design? what is their advantage and disadvantage?

why to use assertions in verification? what is their advantage over plain testing and what is their disadvantage over plain testing?

any help is appreciated.
 

Hi, this paper is pretty good:

**broken link removed**
 

assertion is a verification method for us to find some abnormal sequence very quickly!
 

the main advantage to use assertion to check your design is, this assertion is always present, and then in case you test the sub-module a, you could trig an assertion inside the sub-module b, that's you do not expect.
But after the problem is, when you have add many assertions in each modules/sub-modules, the simulation speed is reduced and you could disable some assertions.....
 

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