Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to do capacitor layout for capacitance of 10pF?

Status
Not open for further replies.

chaitu2k

Member level 3
Joined
Apr 27, 2004
Messages
55
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
501
capacitor layout

hi
i need a capacitor layout for capacitance of 10pF....can anyone give me material of how i should do it...this is the first time i'am doing a capacitor layout..i'am doing iin 1.6u tech
 

capacitor layout

What kind of capacitor you want to use? 2 layera of poly or MOS capacitor, it depends on youe design rule, and youe requirement of accuracy.

I think it cost too much area, no one can help you in dereasing the area, you can use one outside the chip. :)

Good luck!
 

Re: capacitor layout

you can realize it in mos varacter.

lxb97409
 

Re: capacitor layout

The choice on the type of the capacitor, whether it is a poly-poly or MOSCAP type is highly dependant on the application of this element. Please do indicate the purpose of this capacitor?. However MOSCAP could also be used to realize this capacitor since the area consumption is huge. In parallel to piao's suggestion I also think an off-chip capacitor could be used since the value is quite big, furthermore you could also obtain a high Q performance .

Rgds
 

Re: capacitor layout

10p is not very big.
you can use mos cap
 

Re: capacitor layout

I agree that 10 pF is not that big, although i don't know how big they would be in 1.6u technology. Poly-Poly would seem to be the right choice if the tox is not that huge.

Try searching papers on "Fractal Capacitors" and "Flux Capacitors".

The advantage over moscap are that they have higher capacitance, and are more linear.

Let us all know, if it would be feasible to implement them in 1.6u.
 

Re: capacitor layout

for mos cap, the value is about 1.5fF/um^2,10P is 10000fF, so 100um*100um is ok, which is about a PAD or so.

for polytopoly, the value is about 0.8fF/um^2, so 150um*150um is ok.

both of them are not very big.
 

Re: capacitor layout

If you try to reduce the area,you could try fractal capacitor layout
 

capacitor layout

you should find the unit cap value from design technology;then calculate the size
 

capacitor layout

For better quality of Q, try the MIM cap
 

capacitor layout

before you layout you must read the layout rule carefully,the cap's type depands on it
 

Re: capacitor layout

it depends on need if you want very high Q and accurate choose MIM cap...if not can choose mos cap ( mos cap gives hugh capacistance value but process variation very high)
 

Re: capacitor layout

As I have seen you use 1.6um CMOS technology. I do not believe you have a luxury of MIM. Poly-Poly is big one already!
Use MOS cap. The leakage will be small - TOX is huge for these days and linearity will be dependant on voltage. You can simulate it over process/VCC/temp and see how it performs. I would probably limit the voltage range to (gnd+VT) - (VCC-VT) (or even narrower). This should give you decent cap.

You can for sure use it for decoupling - you can put MOS structure under the whole bus.

You are going to save not only area but will have also more space for routing since Poly-Poly caps on older techs. do not allow routing above them.
 

capacitor layout

for voltages from 0-vdd (normal case of cap connected to ground) use PMOS in accumulation. Tie well of PMOS to ground, and use gate as top plate of capacitor. no need to draw source/drain.

i suppose you could use nmos if your process is p-well (pmos drawn in substrate). in that case, use NMOS in accumulation also - well of NMOS goes to higer voltage, and gate connects to ground.

the reason i suggest accumulation is because the capacitance is linear vs voltage applied. inversion, it is very nonlinear as you pass thru threshold, which can do weird things if you need an accurate cap for timing or compensation.

sound good?
 

capacitor layout
 

capacitor layout

you must read design rule first
It's important for layout & design engineer.
 

capacitor layout

hi,

forming a capacitor is pretty easy in layout.
just u have to follow trail and error method.
first draw cap with 10by 10 microns and extract the value.
now create an array to get the required value.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top