How to design pad ring for Two stage opamp

Hi,
I want to design a pad ring for Two Stage OPAMP in Cadence. Can anybody plz help me to design a padring. I dont know how to design of padring.
Thanks

If your process does not provide IO cells for analog and digital IO then you can make up a simple setup, but the possibility of ESD failure might be highly possible. If you dont have them available here is a starting point.

You would first need to know what size pad your bonder can bond too (pad size and pitch). I would start making your pads 100umX100um (pitch i really dont know maybe 100um). Now each pad should be all metal layers with the entire pads being filled with vias going up and down all layers. This makes a strong structure to with stand the bonding process.

On the pads you then have to put down a select layer which will stop the passivation, to keep the pads open for bonding. I think in TSMC its CBblk, you can look in your pdk docs...

Then I would say you need ESD diodes on any high impedance nodes, so your input transistors.

Now this is only the basics, designing real ESD structures and IO rings is very complicated stuff, some people do this full time and thats all they focus on, so there is alot going on here.

I hope this helps

Jgk

Also you need to plan below things,
1. How many power/ground pads you have?
2. How many signal pads you have?
3. Do you have any pads only for testing purpose?
4. What type of package ?

-Dinesh

Hi,
My layout size is 70um x 70um. and it has 6 pins. 1-gnd pin, 1-Vdd pin, and other 4 are signal pins. plz help me in pad designing. I am new to this. Plz tell me what should be Pad size and all the things needed.
Thanks..

Hello Shitu,

I asked you questions above..... You need to know them by asking your professor.. boss... or whoever will be bonding your chip!!!

Jgk