+ Post New Thread
Page 1 of 2 1 2 LastLast
Results 1 to 20 of 22
  1. #1
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    How to Read a file into verilog test bench and pass it to the verilog code

    Hi,

    I need to generate a signal from MATLAB and store the data into a file and then use that file as an input to verilog code.

    i just need to know how to read a file in verilog. and in what format should the file be to be able to be read in verilog.

    can someone please help me with that.

  2. #2
    Member level 2
    Points: 550, Level: 4

    Join Date
    Nov 2010
    Location
    Israel
    Posts
    42
    Helped
    6 / 6
    Points
    550
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    $readmemh() is usful for such tasks.
    It reads text file that contains hex values into array.
    google readmemh to find some examples.


    1 members found this post helpful.

  3. #3
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    thanks for the reply :)
    i have used the same function in the test bench to read the data from the file
    but i am still not able to send the data properly to the code.



    •   AltAdvertisment

        
       

  4. #4
    Member level 2
    Points: 550, Level: 4

    Join Date
    Nov 2010
    Location
    Israel
    Posts
    42
    Helped
    6 / 6
    Points
    550
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    If you could attach the Verlog code and the text file with values, I can try and go over it.



  5. #5
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    i am running the verilog code on quartus II. so i may need to attach the complete project.
    should i do that?



  6. #6
    Member level 2
    Points: 550, Level: 4

    Join Date
    Nov 2010
    Location
    Israel
    Posts
    42
    Helped
    6 / 6
    Points
    550
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    Sorry, I don't have quartus... (I mainly work with Xilinx).
    Maybe 2 files are enough, I will try to go over them:
    1. The test-bench Verilog file, that contains the $readmemh() function call, the array that the values are read into, and the loop that goes over the values in this array.
    2. The text file with the hex values.



  7. #7
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    its not allowing me to attach the .dat file. the dat file is basically a matlab generated file. i ve generated a random signal and saved the values by converting the signal values to binary.
    i have attached the testbench though. i guess there is a problem with the test bench code.
    thanks.



  8. #8
    Member level 2
    Points: 550, Level: 4

    Join Date
    Nov 2010
    Location
    Israel
    Posts
    42
    Helped
    6 / 6
    Points
    550
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    1. I would recommend moving the two $readmemh() lines into the last initial block, just before the for() loop.

    2. The data files should not be binary files, but text files with hex values readable with a simple text editor (like Notepad).
    See example here: http://www.rose-hulman.edu/~doering/...tasks/data.txt

    in your case (16 bit values), the file can look like this:
    1f
    1234
    3d4
    55a3
    0
    9be3

    I'm not familiar with MATLAB .dat file. If they don't look like this, you may need some script or Excel function to convert MATLAB output to the above text format

    3. To debug the file reading thing, I would suggest adding a $display() line inside the for() loop, just after X39[i] = mem_X[i]; to print the D39 and X39 values.

    4. D39 and X39 are 16 bits vectors. You can't index them with i that counts till 2999.

    5. I don't fully understand the Adaptive_LMS_Filter instantiation line. The for() loop starts and ends at time 0, and all the 3000 values go through D39 and X39 during time 0, so after reset is released and clocking starts, the filter will only see a single (constant) value in D39 and X39 - the last value from the file.

    6. If you meant to present the list of values to the filter, a new value in each clock, I guess you should do something like the attached.



    •   AltAdvertisment

        
       

  9. #9
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    Thank You so much for your help



    •   AltAdvertisment

        
       

  10. #10
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    hi yoramgr,

    this time i have to read a 2-D array...

    actually I am processing an image this time. the image is of 288 x 384 x 3 array.

    i have taken the pixel values into a txt file in hex format from MATLAB. and as you told me last time, the values in file are hex values and the file itself is not in hex format.

    now i have to input those values to verilog and process them.

    any suggestions ?



  11. #11
    Super Moderator
    Points: 255,114, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,445
    Helped
    13540 / 13540
    Points
    255,114
    Level
    100

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    I don't use Verilog for testbenches, but in VHDL testbenches , it's easy to read Matlab generated files with general file I/O commands. I guess, it should work with Verilog $fread as well. It's particularly useful, when you want to supply a waveform to a signal processing algorithm, one sample per clock cycle. But you should be also able to write the data to a memory object.



  12. #12
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    Hello FvM,

    thank you for you reply.
    I have not yet used any one of them...but using which of these, readmemh or fread will i be able to read the complete 2D array and store it as a 2D array.
    so that i can process the data by indexing the row and column.



  13. #13
    Member level 2
    Points: 550, Level: 4

    Join Date
    Nov 2010
    Location
    Israel
    Posts
    42
    Helped
    6 / 6
    Points
    550
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    You can define 3 arrays, each 2D (assuming 8 bit for each element):

    reg [7:0] mem_R[0:287][0:383];
    reg [7:0] mem_G[0:287][0:383];
    reg [7:0] mem_B[0:287][0:383];

    prepare 3 files and try to readmemh 3 times. I'm not sure about the file data order (row by row or column by column), but you can try to play around with it, with small array first.



  14. #14
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    man this is getting frustrating...as u had suggested i tried generating 3 different files for R, G and B.

    when i open the text file to check the values the file for G is getting generated properly but for R and B the txt files are showing garbage values.

    so i am going to try with only one file. i cant waste more time in generating the 3 files. do u have any suggestion for that.



  15. #15
    Member level 2
    Points: 550, Level: 4

    Join Date
    Nov 2010
    Location
    Israel
    Posts
    42
    Helped
    6 / 6
    Points
    550
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    Well, you can always gather all the information in one file, first third of the file will hold R values, second third will hold G values, and last third will hold B values.
    Total: file will hold 331776 values (288 x 384 x 3).
    In Verilog, define 3 arrays of 2D, and 1 array 1D:

    reg [7:0] mem_R[0:287][0:383];
    reg [7:0] mem_G[0:287][0:383];
    reg [7:0] mem_B[0:287][0:383];
    reg [7:0] mem_File[0:331775];

    then $readmemh() the file into mem_File array, and add a few loops to copy from mem_File into mem_R, mem_G and mem_B.



  16. #16
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    i have made 3 different files for R, G and B files. now i am just trying to read R the file.

    i hve attached the text file. please check it.

    what might be the error in this code
    module Edge_Detection();

    reg clk;



    integer fd;
    integer i;
    integer r;
    wire [7:0] im_r[110591:0];


    initial
    begin
    fd = $fopen("C:\Users\Rohit\Documents\MATLAB\image_r.tx t","r");
    end


    initial
    begin
    clk = 1;
    for (i = 0; i <= 110592; i = i+1)
    begin
    r = $fscanf(fd,"%b",im_r[i]);
    $display("%b",im_r[i]);
    end
    end

    always
    begin
    clk = ~clk;
    end

    initial
    begin
    $fclose(fd);
    $finish;
    end

    //Edge_Detection ED (clk);


    endmodule


    1 members found this post helpful.

  17. #17
    Member level 2
    Points: 550, Level: 4

    Join Date
    Nov 2010
    Location
    Israel
    Posts
    42
    Helped
    6 / 6
    Points
    550
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    1. To actually store the data in the array, I think you better define im_r as reg, and not as wire.

    2. In the fopen line, there is a space in the filename (between "image_r.tx" and the "t").

    3. There is a common confusion with "binary" contents of a file. When you open image_r.txt file with a text editor, and can see "00000001" etc, then that's a text file, and when reading it in pure binary reading function (like $fread), it will give you the ascii codes of "0" (0x30) and "1" (0x31), and a Line-Feed code (0x10) after each 8 characters.
    For your file format, you better use:
    $readmemb("C:\Users\Rohit\Documents\MATLAB\image_r .txt", im_r);
    instead of $fopen, $fread and $fclose.

    4. To be able to read your debug data in $display, you better change the "%b" to "%h" or "%0h" (that's a 'zero' before the 'h') .

    ---------- Post added at 15:19 ---------- Previous post was at 15:18 ----------

    another minor issue:
    for (i = 0; i <= 110592; i = i+1)
    should be:
    for (i = 0; i < 110592; i = i+1)


    2 members found this post helpful.

  18. #18
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    Thanks a ton yoramgr!!!
    I have used readmemb. I am able to read from a file and write to a file in verilog properly. I have some issues to solve in MATLAB now.
    thanks a lot.

    I didnt have to use for loop for readmemb. it reads the whole file at a time
    for $display i needed to use the loop to show one data at a time.
    same for $fdisplay to write in a file, used a loop.



  19. #19
    Junior Member level 2
    Points: 722, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    23
    Helped
    1 / 1
    Points
    722
    Level
    5

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    one more question yoramgr

    can i use display in a test bench?

    can i pass a 2 - D array from a test bench to verilog code.

    i am trying to send an array of data 8 bit wide and with depth 110592

    its like [7:0] im_b_x[110591:0]



  20. #20
    Newbie level 3
    Points: 414, Level: 4

    Join Date
    Sep 2010
    Posts
    3
    Helped
    0 / 0
    Points
    414
    Level
    4

    Re: How to Read a file into verilog test bench and pass it to the verilog code

    I am also stuck at the same place



    •   AltAdvertisment

        
       

--[[ ]]--