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event driven, cycle based and compiling mode simulators

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cyboman

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can someone explain the differences between these kind of simulators? what are the benefits and drawbacks of each and if you have access to all three what kind would you use and in which situation?

any help is appreciated.
 

Hi, not sure if you had a chance to look at this page:

Logic simulation - Wikipedia, the free encyclopedia

scroll down to: Event simulation versus cycle simulation

Basically, I think of event driven simulators as including timing delays and 1/0/x/z/r/weak/strong signal strengths and cycle simulation as having only 1/0 logic states and no use of individual delays. You need to check the capabilities of your cycle simulator to see what it supports.

---------- Post added at 20:18 ---------- Previous post was at 20:16 ----------

Hi, this page describes compiled versus interpreted simulators:

VERILOG FAQ TOOLS

Scroll down to: What is the difference between compiled and interpreted Verilog simulator ?
 

cycle based simulator are more accurate for timing event!
 

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