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if this is a digital block inside an analog module, you can request to the analog designer, the load/drive capability for each pins and define better constraints.
If you want to add this constraint at pad level, you need to know the PCB used, and every think like this, package....
In general, I only apply the set load/drive only for pin between analog/digital, because, this could have an impact on timing. The pad are so "slow", this constraints do not add much info.
Go conservative.
For set_load, use the max load that a medium or large sized buffer can drive.
Instead of set_drive, use set_driving_cell with the minimum sized buffer.
One approach is to look at what is likely to be driving the ports of your module and what your ports will likely be driving.
During your design review your group may have made the rule that all outputs are registered and all inputs are registered; with exceptions noted.
Is it the Q output of a flop driving the input? Then use a flop/Q as the driving cell.
Are you driving a flop in another module? The use a flop/D as the load.
As far as picking the drive size for the cell types, you can get a list of the quantities of each cell type used in your design and make an educated guess as to what are the likely drive sizes.
Alternatively you could pick medium drive cells as a good guess.
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