Design Compilor Warning LINT-99

My synthesis script is

analyze -f verilog ~/../divider.v
2 elaborate divider
3 uniquify
4 current_design divider
5 create_clock clk -period 12
6 set_clock_transition 0.05 clk
7 compile_ultra
8 check_design

It is giving a waring of "There are 1 potential problems in your design. Please run 'check_design' for more information. (LINT-99)"

I have check the code but unable to fix the problem.
What is the problem in the script?

Did you run check_design? What does the command returns?

Hi, analysis should have provided some feedback on the problem:

For example:
Warning: In design ‘myDesign’, there are sequential cells not connected to any load. (OPT-109)
Information: Use the ‘check_design’ command for more information about warnings. (LINT-99)

What are some of the warnings from analysis?

Can you run check_design and post the warnings?

during compile time it was giving this warning. If i issue check_design after compile it does not give anything. When i refer help it says that we need to reload the design again and issue check_design.

after compile , how to reload and issue check_design

vimedu said:

during compile time it was giving this warning. If i issue check_design after compile it does not give anything. When i refer help it says that we need to reload the design again and issue check_design.

after compile , how to reload and issue check_design

Click to expand...

Hi, the warning you received may have pertained to unused memory elements (flops where the Q/QB are floating). The synthesis tool will remove these elements unless explicitly told not to. You need to run check_design earlier (before compiling) in order to get more detail; try running right before uniquify.

The reason you do not get the warning after compile is that the tool probably remove the offending cells.

Please be sure to understand completely any warnings that come from the synthesis tool. The warnings are telling you that the tool is going to make a decision and the decision may or may not be your intention. It is possible to synthesize gates whose function will not compare to the RTL simulation results; it is not the synthesis tool's problem, it is related to the RTL that comes into the tool.

Send your warnings if you want some feedback.