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sdc constraints in detail

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chanducs24

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hi,

can anyone explain me about SDC constraints..what it contains? how it would be useful in ascii designs?
 

Constraints in general can be divided into two categories, namely, Design Rule Constraints and Optimizations Constraints. Design rule constraints are implicitly defined by the vendor of the library that is being used for synthesizing the design. For example, transition time, fanout load and cap. The optimization constraints are the ones that are given by the designer. For example, clock uncertainity, latency, input delay, output delay, etc. For more details refer the SDC user manual.

Please clarify if my post is misleading in anyway.
 
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Hi bala,

thank u..its good one..i understood

chandra.
 

Like I said the design constraints are mentioned by the library vendor. For example, if the library file contains three types of Wire Load Models namely small, medium and large. We can choose from the three and specify through the SDC file that we would like DC to use SMALL or MEDIUM or LARGE Wire Load Model. Thus SDC file is used to convey the design intent.
 

see synopsys SDC constraints documents ,

SDC is original synopsys format , now is open format , accepted by all vendors ,
 

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