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how to change verilog code to VHDL code

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reef88

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hi,

can someone in this forum convert verilog code to vhdl code..please...

really need others help...

this is the code:

module line_cntr_v(
input CLK_DIV,
input EN,
input RST,
input V_CNT,
output reg H_V_CNT,
output reg V_DONE,
output reg [9:0] V_COUNT
);
reg H_DONE;


always @ (posedge CLK_DIV)
begin
if (RST)
begin
V_COUNT<=0;
V_DONE <=0;
H_V_CNT <=1;
end



if (V_COUNT==520)
begin
V_COUNT<=0;
V_DONE <= 1'b1;

end

else
if (EN)
if (V_CNT)


begin
V_COUNT<= V_COUNT+1;
V_DONE <= 0;
H_V_CNT <= 1;
end



else
begin
V_COUNT <= V_COUNT;
V_DONE <= 0;
end




end



endmodule
 

TO luciferus,

can you be more specific about XDHL...

it is a software?
 

Yes, it's a software, i've never used it, i just know that exists.

X-HDL 4 is the premier Verilog <=> VHDL bi-directional translator. X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, "hand tweaks" of the translated code. X-HDL also contains specialized algorithms which are very effective in translating behavioral-level code to functionally equivalent target-language code.
Click to expand...

**broken link removed**
 

ok..i get it...
i have try that software..but it doesn't support large file in demo version...this software is not free...
any others software that can be used?
 

Do you have any experience with either VHDL or Verilog? The examples that you've given are ridiculously easy. not just that, but when people give you the exact, correct code translation you somehow still have issues. I might understand if you had issues with remotely complex code, or if you were transitioning from C/C++, but that doesn't seem to be the case.

beyond that, the posted verilog code isn't even valid.
 

i'm new with vhdl code...not experience in verilog code...
if you say it is easy...
why not you translate it for me...please...
 

maybe you can do a little effort.
there is four things to do to translate verilog to vhdl
1/find translation module in vhdl. This is just the declaration of your design. If you don't know to do this, you can stop to learn vhdl.
2/transaltion of always statement
3/translation of if statement
4/ translation of data assignement

Five minutes on the web should be enough to find this information.

Regards,
Jerome
 

ok..fine..
i will try my best...

---------- Post added at 20:46 ---------- Previous post was at 20:38 ----------

hi,

i want to ask one question...
how can i define this output code in vhdl code?

output reg H_V_CNT,
output reg V_DONE,
output reg [9:0] V_COUNT

because it has reg...
 

these are first some outputs then declared them as outputs in your entity. It's all.
 

hi...
what is mean this code?

reg H_DONE;

can you explain it...please
 

This is an one bit internal signal named H_DONE.
Please learn a little bit about verilog or vhdl. read some book
I don't think to tranlate something you don't understand is a good approach.
 

thanks in advance to vishwa for the info..
 

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