Translate verilog code to vhdl code...

hi,
can anyone in this forum translate this verilog code to vhdl code...please...

this is the code:

module FSM_COMP(
input [9:0] COUNT,
input [9:0] V_COUNT,
input CLK_DIV,
input RST,
output reg H_D,
output reg H_S,
output reg V_D,
output reg V_S
);

always @(posedge CLK_DIV)
begin

if (RST)
begin
V_D<=0;
H_D<=0;
end


else

if ((COUNT>=12'h90) && (COUNT<=12'h30F))
H_D<=1;

else
H_D<=0;

if ((COUNT>=12'h5F) && (COUNT<=12'h31E))
H_S<=1;

else
H_S<=0;

if ((V_COUNT>=12'h20) && (V_COUNT<=12'h1FF))
V_D<=1;

else
V_D<=0;

if ((V_COUNT>=12'h1) && (V_COUNT<=12'h207))
V_S<=1;

else
V_S<=0;

end

endmodule

Hi,

can anyone in this forum help me check this vhdl code..
it is similar with the verilog code above...
need others help..please

this is the code:

entity FSM_COMP is
Port ( COUNT : in STD_LOGIC_VECTOR (9 downto 0);
V_COUNT : in STD_LOGIC_VECTOR (9 downto 0);
CLK_DIV : in STD_LOGIC;
RST : in STD_LOGIC;
H_D : out STD_LOGIC;
H_S : out STD_LOGIC;
V_D : out STD_LOGIC;
V_S : out STD_LOGIC);
end FSM_COMP;

architecture Behavioral of FSM_COMP is

BEGIN

PROCESS (CLK_DIV)
BEGIN
IF (CLK_DIV'EVENT AND CLK_DIV = '1') THEN

IF (RST = '1') THEN
V_D <= '0';
H_D <= '0';

ELSIF ((("00" & COUNT) >= "000010010000") AND (("00" & COUNT) <= "001100001111")) THEN

H_D <= '1';
ELSE

H_D <= '0';
END IF;
IF ((("00" & COUNT) >= "000001011111") AND (("00" & COUNT) <= "001100011110")) THEN

H_S <= '1';
ELSE

H_S <= '0';
END IF;
IF ((("00000000000" & V_COUNT) >= "000000100000") AND (("00000000000" & V_COUNT) <= "000111111111")) THEN

V_D <= '1';
ELSE

V_D <= '0';
END IF;
IF ((("00000000000" & V_COUNT) >= "000000000001") AND (("00000000000" & V_COUNT) <= "001000000111")) THEN

V_S <= '1';
ELSE

V_S <= '0';
END IF;
END IF;
END PROCESS;

end Behavioral;

try using XDHL

Arithmetic operations (e.g. compare) can't be performed on STD_LOGIC_VECTOR, the have to be performed on either SIGNED or UNSIGNED signals.
But it would be legal syntax with STD_LOGIC_UNSIGNED library in effect.

It don't understand the purpose of this expression
("00" & COUNT) >= "000010010000"
Why not COUNT >= "0010010000"
Unfortunately, the Verilog code is confused in the same way, because it compares
10 Bit variables with 12 Bit constants where it could use 10 Bit constants.

why do you need to translate the code from verilog to vhdl? The eda tools read both languages and in generate all designers are able to read both also.

it's because my project are using vhdl code...

Hi you can use a VCS tool also to simulate your VHDL code.