PIC18 Capture module does not capture rising edge. Compare mod does not toggle output

Hi,

I am using a PIC18F4520 and I am having difficulty using the CCP module. I am trying to capture a clock signal so I am using the Capture function of the module. I have the module set up to run off of TMR3. I also have the CCP1 pin set as an input. The interrupt for the capture works correctly in that the flag is set when the clock input goes from low to high; however the value in the CCPR1 register continues to change while the input is high. So instead of capturing the rising edge of the input, CCPR1 changes with TMR3 while the input is high. So, when I read CCPR1 in the interrupt, the interrupt latency is included in the time value that I read from CCPR1.

I have read the sections of the data sheet many times and I know how the module should work, but I can't seem to work it properly.

I also have a problem with using the compare module. I have everything set up correctly to toggle the output pin on a match. The interrupt is generated correctly when TMR3 is equal to CCPR2; however the CCP2 pin does not toggle and I have to do this manually in the interrupt which makes the signal inaccurate.

Does anyone have any ideas?

Thanks!

you need ECCP . refer to page 149 0f the datasheet.


bit 7-6 P1M11M0: Enhanced PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11:
00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned
as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B1C1B0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are
found in CCPR1L.
bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low

So ECCP doesn't really effect the functionality of the capture module so I'm not sure how the ECCP will help.

The first 4 bits of CCP1CON will be don't care because CCP1M = 0100 or 0101.

Can you please clarify

In 40/44-pin devices, CCP1 is implemented as an enhanced
CCP module with standard Capture and Compare
modes and enhanced PWM modes.

=)

Right, so I'm using the ECCP module. My problem is that it doesn't work like I would expect. What I need is: when the input to the CCP1 pin is transitions from low to high that the timer3 value be saved in CCPR1 at the transition edge of the signal. What is happening is when the CCP1 input is toggled from low to high, CCPR1 begins to capture the timer3 value and continues to update with the changing timer3 value until CCP1 returns low or until I set the CCP1 to capture of the falling edge. So I am not getting the timing value of the signal edge. Any idea why this would happen?