+ Post New Thread
Results 1 to 11 of 11
  1. #1
    Junior Member level 3
    Points: 645, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    31
    Helped
    0 / 0
    Points
    645
    Level
    5

    Using design compiler for synthesis

    Hi,
    I will be using design compiler to synthesize design. My design contains `ifdef-`endif blocks. I can compile and simulate it using synopsys vcs as:

    Code:
    vcs +define+<one of possible value for `ifdef> filename.v
    That would compile and simulate but I can't seem to find how to synthesize it the same way?

    Thanks for inputs

  2. #2
    Newbie level 2
    Points: 403, Level: 4

    Join Date
    Oct 2010
    Posts
    2
    Helped
    1 / 1
    Points
    403
    Level
    4

    Re: Using design compiler for synthesis

    Hi, you can use a .v file include the `define and add this file to sythesis it



    •   AltAdvertisement

        
       

  3. #3
    Junior Member level 3
    Points: 645, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    31
    Helped
    0 / 0
    Points
    645
    Level
    5

    Re: Using design compiler for synthesis

    Thanks bffgot,
    but can u please elaborate a little bit? I've never used include before so I may not get idea easily

    Thanks



    •   AltAdvertisement

        
       

  4. #4
    Newbie level 2
    Points: 403, Level: 4

    Join Date
    Oct 2010
    Posts
    2
    Helped
    1 / 1
    Points
    403
    Level
    4

    Re: Using design compiler for synthesis

    Hi wisemonkey,
    u can add `define "one of possible value for `ifdef" in a define.v file, then add this file to sythesis it


    1 members found this post helpful.

  5. #5
    Member level 2
    Points: 1,471, Level: 8
    dianin's Avatar
    Join Date
    Nov 2009
    Posts
    53
    Helped
    19 / 19
    Points
    1,471
    Level
    8

    Re: Using design compiler for synthesis

    Quote Originally Posted by wisemonkey View Post
    Thanks bffgot,
    but can u please elaborate a little bit? I've never used include before so I may not get idea easily

    Thanks
    You can create one file consists all parameters and then include that file inside the RTL file. For example you have parameter GATED_CLK and WIDTH_CH , define in one file named test_def.v as follow:

    `define GATED_CLK
    `define WIDTH_CH

    you have to include above file inside your RTL file , for example your RTL file is test.v. Add following line inside the test.v:

    `include "test_def.v"
    module test (in, out);
    ----
    --
    ------
    endmodule

    This will work in DC.


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  6. #6
    Junior Member level 3
    Points: 645, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    31
    Helped
    0 / 0
    Points
    645
    Level
    5

    Re: Using design compiler for synthesis

    Thank you very much dianin and bffgot.
    This way it sounds really easy

    Thanks again I'll report in if I happen to hit a block again



  7. #7
    Member level 2
    Points: 645, Level: 5
    chipmonkey's Avatar
    Join Date
    Oct 2010
    Location
    Bangalore
    Posts
    48
    Helped
    18 / 18
    Points
    645
    Level
    5

    Re: Using design compiler for synthesis

    DC supports ifdef in the RTL files.
    you can add your defines just like how you do it in vcs

    add +define+<VALUE> to the read_verilog command



  8. #8
    Junior Member level 3
    Points: 645, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    31
    Helped
    0 / 0
    Points
    645
    Level
    5

    Re: Using design compiler for synthesis

    Thanks chipmonkey,
    Thats wat I was looking for :) Now I can test design with add and finally use include file
    Btw I assume it would be
    Code:
     read_verilog {design files} add +define+<value>
    Or is it
    Code:
    read_verilog {design files add +define+<value>}
    In any case I'll try both. Thanks



  9. #9
    Member level 2
    Points: 645, Level: 5
    chipmonkey's Avatar
    Join Date
    Oct 2010
    Location
    Bangalore
    Posts
    48
    Helped
    18 / 18
    Points
    645
    Level
    5

    Re: Using design compiler for synthesis

    There is no "add".

    command will look like the following:

    read_verilog {design files} +define+<value>

    replace <value> with what you need to define


    1 members found this post helpful.

    •   AltAdvertisement

        
       

  10. #10
    Junior Member level 3
    Points: 645, Level: 5

    Join Date
    Apr 2010
    Location
    San Jose
    Posts
    31
    Helped
    0 / 0
    Points
    645
    Level
    5

    Re: Using design compiler for synthesis

    my bad, Thanks for correcting :).
    I assumed add is a part of command and yes I know about replacing value



  11. #11
    Newbie level 6
    Points: 1,675, Level: 9

    Join Date
    Dec 2003
    Posts
    11
    Helped
    3 / 3
    Points
    1,675
    Level
    9

    Re: Using design compiler for synthesis

    Quote Originally Posted by wisemonkey View Post
    my bad, Thanks for correcting :).
    I assumed add is a part of command and yes I know about replacing value
    In the man page, it is said as below:

    NAME
    read_file
    Reads designs or libraries into memory, or reads libraries into
    the shell.

    SYNTAX
    list read_file
    file_list
    [-define macro_names]
    [-format format_name]
    [-ilm]
    [-library library_name]
    [-rtl]
    [-single_file single_file_name]
    [-work library_name]
    [-scenarios scenario_list]
    [-active_scenarios active_scenario_list]
    [-names_file file_list]

    Data Types
    file_list list
    macro_names list
    format_name string
    library_name string
    single_file_name string
    scenario_list list
    active_scenario_list list

    SYNTAX for lc_shell
    list read_file
    file_list

    Data Types for lc_shell
    file_list list

    ARGUMENTS
    file_list
    Specifies a list of files to read. When specifying more than
    one input_file, enclose the list of names in braces ({}).

    -define macro_names
    Specifies a list of top-level macros for verilog and systemver-
    ilog only.

    So it should be "-define macro_names"



--[[ ]]--