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    test bench in vhdl for set up & hold time violation

    i want test bench in vhdl for set up & hold time violation ,can anybody help me?

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    Re: test bench in vhdl for set up & hold time violation

    First of all, you must use the synthesized netlist, and not the actual verilog/vhdl file you must have written.
    Second, you must have a rigorous input vector of all possible input combinations.
    Something to be highlighted here is that the testing must be exhaustive - which means, many iterations using the input vector, w/o taking time outs between iterations.

    After this, if there are setup and hold violations, you should get some warnings when you simulate using the synthesized netlist.

    I hope this helps.



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    Re: test bench in vhdl for set up & hold time violation

    uselly, the STA is here to check this knid of violations, and I didn't understood why you want to find or to check the setup & hold violation with a testbench?
    As written by ssti85, you need to be very rigorous with your input vectors, and with a timing netlist.



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    Re: test bench in vhdl for set up & hold time violation

    thanks ,but i want the vhdl test bench code because i have to submit it in my assignment



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    Re: test bench in vhdl for set up & hold time violation

    its not very difficult to do that.
    You must have written normal test benches. Just put that in a for loop. and repeat the loop certain number of times (say a avg value of 1000 or so).
    Plus, in each iteration, try to take a different set of inputs. This usually should be done, so you get a better estimate of the the avg. power.

    Else, you can always take the same set of inputs and do all the iterations.



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