Designing switches in SAR ADC

I am designing SAR ADC with 2 GHz clock frequency and I am using charge redistribution technique.Can any body help me how to design switches that charge capacitors in DAC with settling time around 50ps

Well, your gate risetime would have to be way, way less than
50pS for starters. Enough so that the Ron*Csample, times
however many tau equates to your LSB, dominates entirely.
That in turn sets the FET size while Csample is probably
matching-driven (and must be much larger than the variable
FET S/D capacitance). Your switches would want to be
balanced or compensated for minimum charge injection,
which would constrain the architecture to have a minimal
common mode range (more likely, you would be looking at
a differential architecture, but this can be worse for things
like charge injection, when differential switches have
opposite injection due to opposite common-mode position).

Good luck with that 5pS worst case risetime. You may want
to think about how you budget timing for the various phases.

Thanx for ur reply..but i kept my rise and fall times as 1p,but it doesn't work .The voltage isn't reaching to -vin and voltage across capacitor is discharging.Could u plz post me switching cicuit for single capacitor.Thanx in advance

---------- Post added at 08:50 ---------- Previous post was at 08:06 ----------

Thanx for ur reply..but i kept my rise and fall times as 1p,but it doesn't work .The voltage isn't reaching to -vin and voltage across capacitor is discharging.Could u plz post me switching cicuit for single capacitor.Thanx in advance