error in synthesizing the code

hi i am trying to synthesise the code, But its giving me following error. Attached is the code i am trying to synthesise

ERROR:Xst:1769 - Illegal multiplexer construct found in equation of signal <curr_image$mux0064> created at line 163. At least one multiplexer input does not have the correct width. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com.

I think I found the problem : you clearly do not understand digital electronics. you're still trying to write software.

Did you go and read up on digital design yet?

i didnt read any book. can you tell why i am getting that error?

so you're back to impure functions? that didn't work the first time and no one really thought it was a good idea.

I suggest, very strongly, starting over. You are not going to easily solve this problem by throwing different syntax at it. the original problem had _implementation_ issues. In some cases, such issues can be solved by using different constructs. This was clearly not such a case. Rewriting the original design using impure functions, mis-using structural code, mis-using generates, ect... will not fix the problem. Sadly, at one point you were very close to a solution, but gave up when the code had some logic errors. After that, none of your designs seemed to synthesize.

I suggest take _very_ small steps. eg:
1.) design a state machine that reads 1 pixel from image A per cycle. perhaps pixels 0 to 3.
2.) design a state machine that reads 1 pixel from image A per cycle. try pixels N to N+3.
3.) design a state machine that reads 1 pixel from image A per cycle. 0, W, 2W, 3W.
4.) ... N, N+W, N+2W, N+3W.
5.) design a state machine that reads 1 pixel form A. 0 to 3, W to W+3, 2W to 2W+3, 3W to 3W+3
6.) design a ... X to X+3, W*Y+X to W*Y+X+3 ...
7.) now read one pixel from image A, one from image B. these can be read on the same cycle.
8.) perform a subtraction. make note of any latency (inferred registers).
9.) perfrom the subtraction and absolute value.
10.) create a design that accumulates these values.
11.) create a design that _correctly_ accumulates these values per SAD. eg, the current SAD operation should not be affected by the previous or next operations. the accumulator will have a S = S + A state, and a S = 0 + A state
12.) create an "output valid" flag that marks when the output of S is correct.
13.) add any logic for "start", "busy", ect... that would be needed.
14.) use generate statements in the top level module to instantiate as many of these modules as you need (and can fit).
15.) make any design optimizations at this point if needed.

using this method, you will very quickly be able to see what effect your code has. I suggest turning IOB-insertion off and doing synthesis/MAP/PAR runs and looking at what effect the code changes have on resources like slices, BRAMs, and PAR performance. Synthesis will tell you what high-level structures it wants to infer -- RAMs, adders, muxes. MAP will tell you the actual resources used. I suggest adding a ucf with a clock constraint. Then PAR will be able to tell you if the design meets timing.

kakarala said:

i didnt read any book. can you tell why i am getting that error?

Click to expand...

Because you didnt read any book.