Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

NMOS as output buffer and its buffer capacitance

Status
Not open for further replies.

chlee

Newbie level 4
Joined
Jun 15, 2010
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,330
I am using NMOS as output buffer for my amplifier design.
Is the load resistor parallel with the NMOS buffer capacitance in small signal model?
What parameters involved in calculating the buffer capacitance?(Not include parameters which usually ignored)

Sorry for bad english. Urgent help plz...
 

all the capacitances in respect to this buffer node such as Csd, Csg, Csb, and maybe pad capacitance, inculding pin model.
i think you can simply treat it in parallel with Rload in small signal model.
 

Then what exactly is the relationship between the buffer capacitance and those 3 capacitances?
 

buffer capacitance (load capacitance) and those 3 capacitances (parasitic caps) are in parallel, too
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top