why base resistance decreases when emitter width reduces?

why base resistance decreases when emitter width reduces? thanks.

That would be an unusually laid out transistor compared
to what I used to work with. Perhaps the base is ringed
or something.

Book does not give explaination. The resistance for sure would be decided in which direction the current flows. can somone explain this in detail?

Check the early effect or base width modulation in any book.
Check for the reverse biased condition of Jbe (junction -base-emitter)
I have done it long before. So, i have forgot. But here are some pointers to start with, mona.
I am not 100% sure of ans.

But still

When Jbe is reverse biased,
the depletion region between Jbe inc.
the potential barrier across Jbe inc.
As the dep region inc. the width of base (and emitter) dec. (as now a portion gets filled with immobile electoen-hole pairs)
We know the potential barrier opposes majority carrier flow but supports minority carrier flow.
thus, holes from emitter (assuming npn transistor, thus holes in emitter are in minority) gets diffused to base (where they now are in majority)
This is Ib.
Thus Ib increases.
But Ib= Vb/Rb
thus if Ib has increased, it is obvious that Rb has dec.
Thus it comes out as if Rb is decreased. Do cross check from teacher about early effect. And refer good reference books like Electronic devices and circuit theory by boylestad

Any doubt get it cleared from me.. I'll search again

akshay why would one reverse bias Jbe? probably u wanted to say Jcb. i dont think early effect has to do anything with the question I am asking. thanks for thinking though.

Thats exactly what I was thinking.
We know all the conclusions of early effect and varying Vbc and thus Jbc.
And I dont recollect any situation where base resistance decreases when emitter width reduces.
As you said, why would one reverse bias Jbe.
how can there be any possibility of emitter width reducing?
why/when will the emitter width reduce. Lets find out that first. Will post whoever finds t out first.
(But i still doubt the question)

u didnt get the question right..its lateral dimension not vertical..emitter width is always available to u as a variable for design for a given foundry..read the book reference posted by john_blue in this thread, problem is it doesn't give explaination as why...i am looking for the reason..

ok... sure

Most (integrated) transistors are drawn with WE dimension
perpendicular to collector and base current flow so WE ought
to drive down both rb and rc (at least the lateran and quasi-
lateral components thereof).

However I have had occasion to draw transistors where the
base contacts are at the edges of the emitter, so base
current flow is largely parallel to WE dimension (the interest
was minimizing rc in a device with no buried layer, so a dual
collector maximally close to base edge was best). In that
kind of layout

CCCCCCC
B EEEEE B
CCCCCCC

increasing WE would increase rb (particularly problematic
is emitter debiasing). I addressed this by using a "slug"
emitter rather than an arbitrarily variable one, WE being
constrained to a unit cell which is stepped instead of
stretched to prevent dumb choices.

Now, it remains unclear whether this is a "reality" question
or a "model does X" question.

If your model does something that offends common sense,
you should always take that as a clue, and deconstruct
the model parameter derivations.

dick_freebird, I think what your are saying is it depends on the geometry of the transistor but if you read these books you will see that they never talk this with reference to geomtery thats what is confusing me.

Well, I would suggest that first you get clear about whether
this is a measured fact or something on paper / simulated.

Then I would draw out the device features and current
flows for two example cases and decide whether you are
in agreement with the statement.

My personal experience is the opposite of what you say,
so I can't offer you an explanation of why it would be
(generally) true. My point was more that for it to be true
at all, ever, it would require a peculiar construction. Or
a non-standard naming usage of "width" and "length".

Dick_freebird. it appears you have done lot of design and this question is nothing out of my head. Its written in all over the books. This is a perfectly physical phenomenon in BJT. The only problem is I haven't been able to find the reason for it. For example Please click on the book on the thread that John_blue mentioned BiCMOS technology and applications - Google Books Sec. 2.2.4.

It says too "Since the base resistance is proportional to the width of the emitter and inversely proportional to its length narrow emitters with W/L aspect ratios of one third and less are preffered".

I think I understand the reason but want to hear from someone independently.

Please let me know your thoughts.

With P+ surrounding a tiny emitter, for some increase in WE
you might increase Rb. But beyond that I still contend that you
will see Rb come back down, hugely, as the problem decomposes
from the circular-inward to a pair of slab W/L pinched base
resistances (moving from an annular to a dual-base layout
essentially). If your groundrules constrain you to only small
WE, this might look like a straight line, increasing, but I am sure
if you went to (say) WE=20um, LE=1.2um you would have
passed through an inflection.

Maybe we just live in different worlds. When I was doing bipolar
IC design I was interested in amperes and tens of volts. The
emitter they show, is smaller than the contacts I used to use.

possible there may be an inflection point.