Hi all,

I have a very simple memory-mapped AMBA slave module that consists of two registers from and to which can be read or written. I execute the following code to assing some data to REG0 and REG1, however, when checking after
execution both registers have a value of 0x00000000...

// Create aliases for the register file
volatile int *REGFILE0 = (int *) 0xa0000000;
volatile int *REGFILE1 = (int *) 0xa0000004;

void runHelloWorld()
{

*REGFILE0 = 10;
*REGFILE1 = 1021;
}

Here is the code of my slave module. ahbsi and ahbso are records that contain
the AMBA bus signals. Anyone see what I am doing wrong here, maybe a timing issue?

entity testamba is
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;

architecture rtl of testamba is

-- The 2 32-bit registers in the design
signal REG0 : std_logic_vector(31 downto 0) := (others => '0');
signal REG1 : std_logic_vector(31 downto 0) := (others => '0');

begin

ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;

regprocess: process (clk, rst)
variable rdata : std_logic_vector(31 downto 0); -- 32-bit Read Data bus
begin -- process regprocess

if (rst = '0') then -- asynchronous reset (active low)
REG0 <= (others => '0');
REG1 <= (others => '0');

elsif (clk'event and clk = '1') then -- rising clock edge
if (ahbsi.hwrite) = '1' then
case ahbsi.haddr(5 downto 2) is
when "0000" => REG0 <= ahbsi.hwdata(31 downto 0);
when "0001" => REG1 <= ahbsi.hwdata(31 downto 0);
when others => null;
end case;
end if;

rdata := (others => '0');
case ahbsi.haddr(5 downto 2) is
when "0000" => rdata := REG0;
when "0001" => rdata := REG1;
when others => null;
end case;

ahbso.hrdata <= rdata;
ahbso.hready <= '1';

end if;

end process regprocess;