Cadence RTL Compiler fails to do enough incremental optimization at large design

When I synthesize smaller blocks (synthesized to ~200k standard cells) with "synthesize -to_mapped -effort high", everything looks fine. The design gets mapped and many rounds of incremental optimization operation (incr_delay) are done, the final synthesized design is very fast.

Now, I synthesize the top level (should synthesize to ~600k standard cells) all at once with the same script "synthesize -to_mapped -effort high". The designed gets mapped, and only a few rounds of incr_delay are done, the final synthesized design is slow. In the timing report, there are a few critical paths with intermediate devices labeled with (p).
(p) : Instance is preserved but may be resized

Any suggestions on how I could push RTL Compiler to do more incr_delay? Thank you.

Hi zhipeng,
incr_delay is nothing but fixing timing violation on path based. If you see incr_delay is called less time mean.. timing is almost fixed. you will see very less n prefix instances in design..

I cant understand ,why u want to call incr_delay many times..

Hi aravind,
Thank you for the reply. The problem is, when I synthesize the top level, it runs with few incr_delay, but timing is not fixed...

When I synthesize module A or B, many rounds of incr_delay in the log, at the end timing is almost fixed, critical path delay is about 400ps.
When I synthesize a top-level module (consists two module A and one copy of module B), the critical path is the same, only a couple of incr_delay operations were run, at the end timing is not fixed well, many instances along the critical path are (p), critical path delay is about 700ps.

Hi Zhigeng,
I cant tell u clearly , why -700ps delay appearing in top level. there may be many reason on it..
In cause if u turned-on set_attr tns_opto true / .. u can try switch off this.. and do resynthesis. This will focus to reduce WNS ..
Also try to use latest RC10.1 version..

Best of luck..