VHDL entity - Default values to out port signals in entity at power on

kkiran345 · Sep 27, 2010

Hi... i am learning vhdl...
i have written a code for fpga in vhdl, (i have done only simulation)
it receives input serial data with clock and depending on the input, certain pins in fpga are made high or low.
When i simulate, initially all output pins are shown as 'U' ie., uninitialized...
but i want some default values on out pins at power-up / reset of fpga, ie., even before i start sending data to fpga...

FvM · Sep 27, 2010

This is a question of the FPGA hardware features rather than of VHDL syntax. In simulation, all registers are assumed unitialized 'U' on simulation start. In almost any FPGA family, they are initialized at power on, the default state is usually '0' but can be changed by specifying an initial value in the signal definition. Using an initializer is also the way to achieve identical power-on behaviour in simulation and with with the real chip.

You should notice however, that the initial signal state gets effective after start of FPGA user mode respectively configuration load. Before it, all pins have a default inactive state, usually set by a weak pull-up resistor. Check your FPGA hardware manual to learn about the details.

kkiran345 · Sep 28, 2010

Thank you FVM...
i will go through the FPGA manual.

you have specified about initializer... is it possible to initialize signals that are defined in port of an entity.
what is initializer?

FvM · Sep 28, 2010

what is initializer?

signal myreg: std_logic := '0';

is it possible to initialize signals that are defined in port of an entity

Yes, you can write an initialization also in a port definition. But, it will be only effective as long as the port isn't driven by another signal.

kkiran345 · Sep 29, 2010

Thank you i will try it today...
i got some basic doubts...
how to create modules for a design in vhdl... can a package be treated as a module... if so, is it a good idea to import a package with the top-level vhdl code for synthesis.

TrickyDicky · Sep 29, 2010

A package is not a module, but in it you can define constants, functions and procedures. Basically it contains useful stuff that you use in several places.

The only things you can synthesise are entity/architecture pairs.

shitansh · Sep 29, 2010

In addition to initialize registers you can use Flipflops with asynchronous reset, on most of the board power on reset mechanism exist, so by using flip flop with asynchronous reset your problem will be solved.

HTH,
Shitansh Vaghela

permute · Sep 29, 2010

Async resets have always had the issue of asynchronous deassertion. What this means is that, when skew is taken into account, some registers can come out of reset on different cycles. For high speed designs, the systems might come out of reset several cycles apart in which case it could fail every time. For low speed designs, the circuit might just fail sometimes. The slower the design, the lower the probability of failure.

kkiran345 · Sep 29, 2010

Thank you...
but i am a beginner.. this is my first time into synthesis....
till now i have done only simulation, using functions, procedures, packages & components...
could u suggest some books... (synthesizable statements, creating modules and including them into top-level code, dealing with clocks/delays)

thanks in advance...

TrickyDicky · Sep 29, 2010

permute said:
Async resets have always had the issue of asynchronous deassertion. What this means is that, when skew is taken into account, some registers can come out of reset on different cycles. For high speed designs, the systems might come out of reset several cycles apart in which case it could fail every time. For low speed designs, the circuit might just fail sometimes. The slower the design, the lower the probability of failure.

BUT:
At least with qua rtus, it determines the power-up value from the aync reset path in the code. Then, assuming you have no real need for an async reset, just tie it to '0' at the top level. It means you dont have to put attributes all over the place.

---------- Post added at 17:21 ---------- Previous post was at 15:58 ----------

kkiran345 said:
Thank you...
but i am a beginner.. this is my first time into synthesis....
till now i have done only simulation, using functions, procedures, packages & components...
could u suggest some books... (synthesizable statements, creating modules and including them into top-level code, dealing with clocks/delays)

thanks in advance...

Nowadays, its easier to understand what is not synthesizable than what is, as well as referencing the coding templates for infering various building blocks (like rams, multipliers etc).

The things you cannot synthesize:
wait statements.
"after" statements. eg. a <= b after 10ns; The "after" bit is usually ignored. basically anything to do with fixed periods of time.

The basic template for synchronous circuits is:

Code:

process(clk, reset) --leave out reset if you want
begin
  if reset = '1' then
    --reset your signals here
  elsif rising_edge(clk) then
   --do stuff here
  end if;
end process;

Basically, any code is acceptable. But you have to remember you are describing hardware, not writing software. So always make sure you understand the underlying logic. You can write a load of code that will synthesise, but if you dont understand the logic behind it, you wont get very good performance.

Altera Code templates here:
https://www.altera.com/literature/hb/qts/qts_qii51007.pdf

FvM · Sep 29, 2010

At least with Quartus, it determines the power-up value from the aync reset path in the code. Then, assuming you have no real need for an async reset, just tie it to '0' at the top level.

The below example follows your suggestion, as far as I understand it. It sets output q to '1' in an asynchronous reset path. The reset signal is tied to '0' in the top entity. What do you expect as actual initial state of output q?

Actually it's '0', as predictable in my opinion. You have to add an initializer q: std_logic := '1' to change it. Do you understand why?

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reset_test is

  port 
  (
    clk : in  std_logic;
    d    : in  std_logic;
    q    : out std_logic
  );

end entity;

architecture rtl of reset_test is
signal reset:  std_logic := '0';
begin
   process (clk, reset)
   begin
      if reset = '1' then
         q <= '1';
      elsif rising_edge(clk) then
         q <= d;
      end if;   
   end process;
end rtl;

shitansh · Sep 30, 2010

permute said:
Async resets have always had the issue of asynchronous desertion. What this means is that, when skew is taken into account, some registers can come out of reset on different cycles. For high speed designs, the systems might come out of reset several cycles apart in which case it could fail every time. For low speed designs, the circuit might just fail sometimes. The slower the design, the lower the probability of failure.

Perhaps for that most of engineer prefers Async reset assertion and Sync desertion. And always clock and reset will be routed on global network so there is minimum skew on these nets compare to others.
And initialization of registers also done with this!!

FvM said:
The below example follows your suggestion, as far as I understand it. It sets output q to '1' in an asynchronous reset path. The reset signal is tied to '0' in the top entity. What do you expect as actual initial state of output q?

Actually it's '0', as predictable in my opinion. You have to add an initializer q: std_logic := '1' to change it. Do you understand why?

Hi FvM,

In most of the board there is power on reset circuitry always present, so when board powers up there will be reset pulse due to capacitor charging and discharging so initial state of q will be 1, dont you thing?
Please clear me if i miss some thing.

FvM · Sep 30, 2010

so when board powers up there will be reset pulse due to capacitor charging and discharging so initial state of q will be 1

Yes, if the reset signal is actually connected to a reset source and asserted at power on. The example however ties reset to '0' to implement a suggestion from a previous post. In this case, the reset path is completely removed from the synthesized logic and the default '0' power on default gets effective.

TrickyDicky · Sep 30, 2010

I have tested it with an input reset port rather than internal signal, and that port is tied to '0'. Then it will powerup with a value '1'.

FvM · Sep 30, 2010

Yes, if the reset input is exposed as port, then q will power up to '1'. "just tie it to '0' at the top level" is different from "connect it as port signal and short it to ground" in my opinion. But if you meant the latter, you are right, of course. Apart from consuming pin resources this way, I still think that a standard VHDL initializer is more easy, if you don't need an explicite reset option. At least it involves less lines of code. And it gives consistent results between simulation and synthesized hardware. An inactive reset will still leave the signal at 'U' in simulation.

TrickyDicky · Sep 30, 2010

I was thinking of just shorting it in the port map (and this works):

Code:

UUT: entity work.my_entity
port map (
clk => clk,
reset => '0'
...
);

FvM · Sep 30, 2010

I was thinking of just shorting it in the port map (and this works):

It does not work in my test. There's no different result between different methods that disable the reset path before synthesis. How do you check the initial state of the register?

P.S. Here's the code:

Code:

library ieee;
use ieee.std_logic_1164.all;
entity reset_test is

  port 
  (
    clk    : in  std_logic;
    d      : in  std_logic;
    reset : in std_logic;
    q      : out std_logic
  );
end entity;

architecture rtl of reset_test is
begin
   process (clk, reset)
   begin
      if reset = '1' then
         q <= '1';
      elsif rising_edge(clk) then
         q <= d;
      end if;   
   end process;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
entity reset_test_top is

  port 
  (
    clk : in  std_logic;
    d    : in  std_logic;
    q    : out std_logic
  );
end entity;

architecture rtl of reset_test_top is
begin
reset_inst: entity work.reset_test
port map  (
    clk => clk,
    d => d,
    reset => '0',
    q =>q
);
end rtl;

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