2P4M 0.35um process TSMC mixed signal

tsmc 0.5u design rule

Hi,

Can anyone help me understanding why 2nd poly is afterall needed? Also wht is the maximum w/l that can be drawn for this particular process? Pls also tell me wht is minimum w/l value acceptable.

Can anyone upload device formation document for TSMC 0.35u 2P4M process.

Thanx,
Gold_kiss

0.35um process

Usually in mixed mode process second poly is used for POLY-POLY capacitors.

tsmc 2p4m

Sometimes Poly2 layer is used for high poly resistors (1..3 KOhm/sq)

tsmc 0.35 process

Weird,
Why can't I find high poly-2 resistor(1.3k ohm/sq) but 50 ohm/sq instead from spice model??

Yes, poly-2 can be used to form PIP capacitor, please check spice model document released by tsmx.

Regards,

design rule checker for 0.35u technology

1. for TSMC 0.35u u can use the TSMC 0.5u high poly2 resistor model (1KOhm/sq).
TSMC 0.35u design rule has high ploy2 resistor's design rule.

2. I meant 1KOhm/sq ... 3KOhm/sq.
Some foundry (VIS Corp.) close to TSMC provide high poly resistirs up to 3 KOhm/sq

tsmc 0.35um design rule

Thanks for updated...

Since there does exist high poly-2 resistor in design rule, how to differentiate low and high one in process?? Add an extra dummy layer or customize??
Is this risky to be used?? There is no any reference can be found...

Regards,

tsmc 0.35um process

They use special Cap-Oxide (CAP) mask layer to distinguish high and low resistivity poly2 layer.
For 0.5um, several months ago they (VIS Corp.) covered high poly2 by CAP layer, but now they use CAP layer to cover low poly2.

So, it's better to clarify this design rule.

0.35um sheet resistance

Can anyone help me understanding why 2nd poly is afterall needed? Also wht is the maximum w/l that can be drawn for this particular process? Pls also tell me wht is minimum w/l value acceptable.

Can anyone upload device formation document for TSMC 0.35u 2P4M process.

Thanx,

Hi Gold kiss,

The TSMC 0.35u 2P4M technology is actually modified from CMOS 1P4M salicide recently. The second poly is for PIP cap usuage. Also you can take it as a poly resistor. The HSR (high sheet-resistance resistor) is not supported in this technology, since there is no salicide or no-salicide difference either in poly1 or poly2 on this technology. If you ask why, I'd say this is originally a process for digital design. I don't think TSMC do put much effort on this technology for analog or RF purpose. If you're not sure how to draw the cap correctly, I suggest you to find the design rule for this technology. What I remember from the lvs file, cap is only defined in region POLY1 AND POLY2. As for poly2 resistor, I guess they're all salicide and you really don't have to think too much on drawing this layer. Just take it as a 50ohm-square resistor. Concerning the W/L ratio, you should notice first your supply voltage. Since the oxide thickness is different for 5V and 3.3V in this technology, don't use 5V devices if your supply won't exceed about 4V(for matching and speed issue). 20/0.35 and 0.4/20 should be allowed. The model for width lager than 20um is from math results, not fitting that well as those from 0.4~20um. Don't try to believe the simulation results if you use width lager than 20um. Though TSMC's manual could provide this value to 200um. Cliff

tsmc spice model 0.35um mixed signal 2p4m

Hi can any one tell me how to write TT case for 350nm TSMC 2P4M process parameter models.......with wmin=0.4um,wmax=2um,lmin=0.35um,lmax=any