fenfei
Member level 1
The specification are:
output frequency:1100MHz ~1650MHz ;
frequency step :1kHz;
switching time:<100us;
spur:<-65dBc;
PN: <-85dBc/Hz@1kHz
<-95dBc/Hz@10kHz
<-105dBc/Hz@100kHz
application: handset(so It's must be very small)
I have designed a 1100MHz~1650MHz frequency synthesizer by two fractional PLL working in pingpong mode to get fast swiching time .But It's too big, and not fit for handset.
Does any one could give me some suggestion ?
output frequency:1100MHz ~1650MHz ;
frequency step :1kHz;
switching time:<100us;
spur:<-65dBc;
PN: <-85dBc/Hz@1kHz
<-95dBc/Hz@10kHz
<-105dBc/Hz@100kHz
application: handset(so It's must be very small)
I have designed a 1100MHz~1650MHz frequency synthesizer by two fractional PLL working in pingpong mode to get fast swiching time .But It's too big, and not fit for handset.
Does any one could give me some suggestion ?