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MOS device theory related questions

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Brittoo

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Hello all

Here are some of my doubts:
1.Why does carrier mobility reduce with temperature for pmos/nmos?

2.Why do low Vt devices have high leakage?

3.Why does the voltage drop happen when the nmos is used to generate a logic "high"?

4. Why do series connected "n" number of nmos/ pmos have a threshold drop of just Vdd -Vth and not Vdd -n(Vth)?

Regards
Brittoo
 

ad 1. The essential effect arises from lattice scattering, which results in a temperature dependency of µ ~ T^(-3/2), see any book on semiconductor physics. The actual mobility temperature dependency of modern CMOS processes is very close to this behavior.

ad 2. The subthreshold or weak inversion swing is about 90 mV/decade, i.e. for every 90 mV of Vgs decrease, the drain leakage current is reduced an order of magnitude. With low Vt devices, at Vgs=0 the leakage current is much higher than for high Vt devices.
 

Hello erikl

Thanks for the reply. Could you please upload any docs related to point #2?

Regards
Brittoo
 

Brittoo said:
Could you please upload any docs related to point #2?
Click to expand...
See e.g. David Binkley: "Tradeoffs and Optimization in Analog CMOS Design", p. 81 below:
 

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