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2nd September 2010, 10:05 #1
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distributed voltage controlled oscillator design
Hi! I recently designed a distributed VCO with hybrid (discrete components + transmission lines) following the guidelines in SkvorDivina paper (reference[1,2] is provided below) in the range 12 GHz, that worked good enough, meeting the design requirements in terms of frequency of operation (apart from a 10% shift due to some inconsitency in the models for discrete devices) and output power.
Well, problems arose in designing a VCO in the band from 1.5 to 5 GHz using the same topology of [2], employing only transmission lines. From nonlinear simulation results, with HB in Agilent's ADS the circuit is capable of attaining oscillations, however, when measured it gives very different results and the oscillation frequenc. are totally deranged. Could it be an impedance matching problem? Did any of you have a previous experience with this kind of circuits and with its simulation?
Thanks!
Reference:
[1] Divina, L.  Škvor, Z.: Experimental verification of a distributed amplifier oscillator. In: Conference proceedings of the 25th European Microwave Conference, pp. 11637, Nexus, Bologna 1995
[2]Divina, L.  Škvor, Z.: Distributed Oscillator at 4 GHz. In: IEEE MTTS International Microwave Symposium Digest, part II, pp. 8658, IEEE MTTS, Baltimore, červen 1998 /Distributed Oscillator at 4 GHz. IEEE Transactions on Microwave Theory and Techniques 46(1998)12, pp. 22403.Last edited by alexdesigner; 2nd September 2010 at 14:07.

2nd September 2010, 11:26 #2
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Re: distributed voltage controlled oscillator design
As is mentioned in the posted document this oscillator is strongly affected by mismatches caused by the transmission line.
Generally the linear or HB simulation doesn't show all the phase changes vs frequency caused by a real TL. Ideally would be to do an EM simulation including TL and component footprints and parasitics.
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2nd September 2010, 13:55 #3
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Re: distributed voltage controlled oscillator design
Thanks for your answer!
did you ever actually try to build or at least simulate one? It is very interesting what you're saying, I've always felt that there's so many degrees of freeedom and unknowns, it turns out to be a difficult task in accurately predicting the oscillating frequencies.
Do you have some more suggestions?
Regards.Last edited by alexdesigner; 2nd September 2010 at 14:04.

2nd September 2010, 18:43 #4
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Re: distributed voltage controlled oscillator design
I built distributed VCO's using TL, but not such wide band as you are looking for. At this wide bandwidth any major phase change introduced due to the distributed nature of the delay element (transmission line) increase the possibility of multifrequency oscillations within the oscillator resonant circuit frequency bandwidth. Also phase changes introduced by SRF of lumped components should be taken into consideration.
From experience I found that the widest bandwidth VCO I got using minimum number of components, especially on the feedback path.
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2nd September 2010, 20:32 #5
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Re: distributed voltage controlled oscillator design
I thank you a lot!
I'm sure you have already seen it, anyway I'll post the second reference as an attached file...my circuit looks pretty much the same as the one described in this paper, in terms of topology. Differences are :
1) I used a fixed width for the gate lines/ drain lines but slightly different spacing between each stage (trying to achieve a tradeoff between a "very short" circuit to raise the maximum frequency, and a feasible design, leaving room for soldering pads etc..) whilst in the document the feedback line is wider, and proceding towards the output width of the lines is decreasing
2) I designed the last section in a simmetric way (mderived half section with a higher impedance in series , representing the L and an open stub representing the C) whilst the author of the paper (Z. Skvor) "put" different sections in his circit for the drain/ gate lines ...and i don't know if this has been found out by reasoning (how?) or by experimental tweaking...
3) different transitor (NE3210S01) , and different substrate Arlon 25 N (eps= 3.38, delta= 0.0025, H=20 mils (0.52 mm))

2nd September 2010, 22:31 #6
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Re: distributed voltage controlled oscillator design
From the paper above seems the difference could be from using a "Periodically Loaded Transmission Line" concept.
I don't know how this concept behaves in real life, or how repeatable is at microwave frequencies because is using also lumped components.
Here is what I found about this:
http://www.waves.utoronto.ca/prof/mo...P_S%20Ohio.pdf
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3rd September 2010, 11:13 #7
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Re: distributed voltage controlled oscillator design
Yes! exactly what I meant, difference between theory/ simul. and real life behaviour. I just measured my oscillator, and i had very different results from what i've been simulating, and the individual frequencies are more affected by transistor parasitics than "the loaded transmission line" i guess!
Thanks for replying me!

14th September 2010, 22:40 #8
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Re: distributed voltage controlled oscillator design
Hi again! There are some topics I'd like to discuss with you all, relating to the DVCO descibed in the last paper I've attached. The "periodically loaded transmission line" is used as an analythical framework in distribuited amplifier theory. In fact, in its essence the distributed tunable oscillator referenced in the post of 09/02/10 comes from a distributed amplifier in which a feedback path is created, and frequency variation is attained by varying in some way the bias point of two active devices at a time.
For describing the input / output relationship analytically in a distributed amplifier one makes use of linear models (small signal) models for active devices, which are modeled as two port networks. The input port of a common source HJFET (neglecting the losses) and the reverse feedback (unilateral approximation) could be seen as an equivalent LC series circuit being C the "stray" capacity between gate and source (Cgs) and L the parasitic inductance at the gate Lg (actually the order of the circuit to take into account more details could be higher than 2, it is just an approximation!!). Same story looking into the output port, but this time we have different paramenters, Ld (drain parasitic inductance) and C= Cds (stray capacitance between drain and source) and of course a VCCS (voltagecontrolledcurrent source) modeling the transconductance gain.
To obtain a distributed amplifier, we arrange the active devices in the following manner. Consider the signal generator coupled to the input line ( a microstrip line) properly terminated by a matched impedance. Now let's "tap" periodically the signal from the input line (gate line) by having the transistor gates connected to it, periodically in space (mantaining the spacing between the stages constant), and the same applies to the drains in the ouput line. Provided the elctrical lenghts between stages is the same for the output and for the input line, this topology gives roughly N times the amplification factor of only one stage, BUT WITHOUT bandwidth decreasing.
From the description above, it seems logical to think at distributed amplifier as two periodically loaded transmission lines, coupled via the transconductance of the active device.
In an oscillator, in particular the one descirbed in the paper above, we create a feedback path by removing one termination and connecting together drain and gate line.
To ensure proper operation, the line impedance should be matched "everywhere" with the load impedance (as matched as possible, to prevent the circuit from having erratic behavior). This could be accomplished by placing addtional "padding" capacitors to the ground and playing with the line widths between each stage.
Now finally the question. Do anyone of you know (or guess) why in the circuit described by Skvor
http://www.waves.utoronto.ca/prof/mo...P_S%20Ohio.pdf:
1) the feedback line has a larger width? Is it perhaps for having a small impedance path?
2) the line widths are decreasing proceeding from the first to last stage? Is it for forcing the signal to go "reverse"?
3) the last sections in the gate and in the drain line look so skewed? Has something to do with killing some unwanted oscillations?
Thank you so much!!

2nd May 2013, 06:56 #9
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Re: distributed voltage controlled oscillator design
I've just seen this post. Maybe it still interesting for you. I have a master thesis with the ADS simulation circuits and practical measures. There is also a paper about it:
Dissertation:
http://www.teses.usp.br/teses/dispon...1034/ptbr.php
Paper:
http://ieeexplore.ieee.org/xpl/login...mber%3D1580066

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26th May 2013, 17:19 #10
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Re: distributed voltage controlled oscillator design
Hi,
are you the author of the MSc. Thesis?!! Pleased to meet you, ALexandre!! (My name's is also the same!!); I've read your thesis a long time ago, and I mentioned your paper on my PhD dissertation (I'll have the viva voce in a month or so!!) .
Thank you for replying anyway!! I remember this circuit almost drove me crazy!! was it the same for you??
Regards,
Alessandro.
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