Confusion relating to the PSRR of LDO

In general, to achieve good PSRR of a circuit, the circuit should be better shielded from the power supply, in other words, this circuit should better have a stable performance despite of the changing power supply voltages

But for a LDO, to get a good PSRR. I think this means that, when the input voltage on the source of a PMOS power transistor is changing, the gate voltage(the output voltage of the error amplifier) should be able to follow the change of the source voltage to get a stable output at the drain of the power transistor

>>>so this means that the error amplifier should follow the power supply change. Otherwise if the power supply has ripples, but the gate of the power transistor is constant, very bad PSRR will be gotten.

Now I am a little confused about this post, to improve PSRR is to shield the error amplifier from the power supply or to make the power amplifier follow the power supply change?

Another question is, PSRR in which frequency range is interesting for us? On different data sheets and papers, different frequency ranges are given, sometimes several KHz, sometimes, several MHz?

Re: PSRR of LDO?

Regarding your first question, both the power transistor and the error amplifier are usually connected to the supply. One possible method of increasing the PSRR of the LDO is by adding a capacitor at the output of the power device (where your regulated voltage should be) to filter out any possible ripples in the output of the error amplifier that could disturb your final output. In addition, the error amplifier itself should also be shielded from the supply through a capacitor.

Regarding the second question, the frequency range of interest is dependent on the application that the LDO is designed for. This is why the frequency ranges are different on the different data sheets

Re: PSRR of LDO?

ammarzouk said:

to filter out any possible ripples in the output of the error amplifier that could disturb your final output. In addition, the error amplifier itself should also be shielded from the supply through a capacitor.

Click to expand...

That exactly what I am confused about.

Let's say, if the error amp is shielded perfectly from the power supply ripple, than the error amp will have a stable output>> The gate of the power transistor is stable

But on the other hand, the source of the PMOS power transistor which is connected directly to the power supply has ripples

---so it seems like the PSRR will be worse

Re: PSRR of LDO?

this is why you also put the capacitor at the output of the transistor; to further stabilize your regulated output

Re: PSRR of LDO?

Electronicmember said:

In general, to achieve good PSRR of a circuit, the circuit should be better shielded from the power supply, in other words, this circuit should better have a stable performance despite of the changing power supply voltages

But for a LDO, to get a good PSRR. I think this means that, when the input voltage on the source of a PMOS power transistor is changing, the gate voltage(the output voltage of the error amplifier) should be able to follow the change of the source voltage to get a stable output at the drain of the power transistor

>>>so this means that the error amplifier should follow the power supply change. Otherwise if the power supply has ripples, but the gate of the power transistor is constant, very bad PSRR will be gotten.

Now I am a little confused about this post, to improve PSRR is to shield the error amplifier from the power supply or to make the power amplifier follow the power supply change?

Another question is, PSRR in which frequency range is interesting for us? On different data sheets and papers, different frequency ranges are given, sometimes several KHz, sometimes, several MHz?

Click to expand...

‘Shield the error amplifier from the power supply’ does not mean to make EA output stable against GND, but against VIN, so your 2 questions which look incompatible is exactly the same.

PSRR of LDO?

In a PMOS LDO if the pass transistor gate is "shielded" from supply,
static-gate vs moving-source produces a strong local gate signal.
You really need to "shield" the pass FET gate from GND and
bypass it to VIN. If you did this ideally, you would have no
"secondary multiplication" of VIN signal, only the baseline
isolation will remain. That is, Coff/Cfilter worth of input supply
signal will pass to the output.

LDOs will tend to have a high Coff with low Ron. The high
frequency PSRR will depend on the C ratio, as-degraded by
output filter cap ESL/ESR. Many LDOs require a specific range
of ESR for stability, though, and you may not be able to use
as stiff a filter as you'd like (possibly having to use a second
stage, like wire-and-bead, filter).

Your PSRR frequency range of interest includes at least the
first few harmonics of whatever upstream switching power
supply there might be. You might call it 1MHz as a round
number.