milesmcgee
Newbie level 2
I'm currently trying to learn how to use TetraMAX to generate test patterns, but have come across a problem when using VHDL.
I have a simple benchmark circuit implemented in both VHDL and Verilog. When I run the Verilog design, TetraMAX creates a list of 50 faults, but when I use the VHDL design of the same circuit it only comes up with 14.
I have run several different VHDL files and have concluded that it is ignoring any internal structure and producing stuck at faults for only the inputs and outputs (generating twice as many faults as there are input and output ports).
is there a specific way in which internal signals must be defined in VHDL in order for TetraMAX to recognize them?
Thanks!
For reference, my VHDL file is as follows...
I have a simple benchmark circuit implemented in both VHDL and Verilog. When I run the Verilog design, TetraMAX creates a list of 50 faults, but when I use the VHDL design of the same circuit it only comes up with 14.
I have run several different VHDL files and have concluded that it is ignoring any internal structure and producing stuck at faults for only the inputs and outputs (generating twice as many faults as there are input and output ports).
is there a specific way in which internal signals must be defined in VHDL in order for TetraMAX to recognize them?
Thanks!
For reference, my VHDL file is as follows...
Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity benchmark is
port (
In1 : in Std_Logic;
In2 : in Std_Logic;
In3 : in Std_Logic;
In6 : in Std_Logic;
In7 : in Std_Logic;
Out22 : out Std_Logic;
Out23 : out Std_Logic);
end benchmark;
architecture benchmark_a of benchmark is
signal wire11 : std_logic;
signal wire10 : std_logic;
signal wire19 : std_logic;
signal wire16 : std_logic;
begin -- benchmark
wire11 <= (In3 NAND In6);
wire10 <= (In1 NAND In3);
wire19 <= (wire11 NAND In7);
wire16 <= (In2 NAND wire11);
Out22 <= (wire10 NAND wire16);
Out23 <= (wire16 NAND wire19);
end benchmark_a;
