How to optimize the load transient response of a LDO?

Hello everyone,

now I am trying to optimize the load transient response of a LDO.

But it seems like it is difficult to achieve good gain and enough phase margin at the same time in the feedback loop.

I tried to increase the gain to improve the load transient response.
But if the phase margin is not enough, the load transient shows ringing, which makes the response worse.

I am wondering are there any suggestions on how to improve the gain and the phase margin at the same time?
How much loop gain would be enough for a LDO?
If it is not possible to make a good gain and good phase margin at the same time, how shall I make the tradeoff?

One big problem is in how the output stage gain swings with
headroom. Your final gain once you get into linear region is
about nothing, so you need a high gain amplifier in front of it
that then needs a pretty low frequency pole, that fights step response.

One approach I have seen, is a split loop. One part high gain,
low frequency (to get DC accuracy) and another with high
bandwidth and limited "authority" that makes the dynamic
operation crisp (settles fast and can maintain setpoint while
the slow loop settles over a longer time).

You may also find some help in a compensation network that
changes C based on output FET headroom and gate drive.
A fixed Miller capacitance may not be what's best.

If you think your output rings now, wait until you model the
details of your output capacitor....