LVDS Bus ... suitable?

Hi, i need to implement a network with a master and several slaves. Basicaly a real time sensor network. The max distance between Master and slaves is 3m. Would LVDS be suitable for my aplication. I could read at a TI AN that is possible to make a LVDS multdrop with one driver and many receivers... How reliable is that? I would be using twisted pair. There is no chance to 2 nodes on network talk at same time becouse the slave just answer when master ask something...

Thank you!

As far as I remember there is a special version of LVDS for multiple loads: B-LVDS

I dont know how good TI note is. But I was very happy with application note I sent to you. At page 17 you can see B-LVDS can support up to 32 Loads.

Cheers

Hi,
As I remember, by your LVDS system is not the 32 sensors are a problem, but the distance of 3 m_ because I know so that its for less as 1 meter specified...
K.

First of all thank you very much.. very good AN from National. The AN from TI is this one https://focus.ti.com/lit/an/slla127/slla127.pdf .
There is another one with number of loads.. but i dont think i will have problems... My next question is... how can i drive the tranceivers as fast a sthey can? Becouse i am using RS-485 with a 32Mbps tranceiver with no problem and my actual neck is the UART and not the tranceiver... the only that can drive the tranceiver as fast as it can is the master of the Network, a FPGA. But all slaves are MCUs or DSPs... I could not find any that could transmit that fast.. How am i suposed to make a fater async transmission? Is there any external hardware? OR MLVDS is not suposed to be used async? The only option i found was to use SerDes and DesSer LVDS, but i dont know if i could use them as M-LVDS and how am i suposed to know when i have some incoming message if there wont be any start bit? Any sugestions?

Thank you!

For data rates above about MBPS, synchronous transmission would be more suitable than asynchronous. Formats that allow easy clock recovery, e.g. manchester encoding or 8b/10b codings are most popular.

But with processors, you're restricted to transmission formats, that are supported by the respective hardware. In addition, the processor's data throughput sets at limit to the data rate. Regarding external hardware, I would think first of dedicated asynchronous and synchronous communication processors.

Hmm, how am i suposed to send a clock for sync comunication.. Any sugestion of communication processor?

Thank yoU!

Hi,
I think Clk is to embed in such comm. serial format/coding ...
K.

Any sugestion of communication processor?

Click to expand...

What's the intended data rate?

Something like 50Mbps - 100Mbps.. My actual one is 20Mbps with a MAXIM external UART and RS485 tranceivers. Its very reliable so far... At the actual situations its enough speed, but i want to make some improvments.

I guess, you won't find faster UART controllers than MAX3107. But it has to be interfaced serially itself, so I wonder if the overall throughput to a uC/DSP will be increased.

With a bus architecture, address decoding and data filtering in the hardware interface (as performed e.g. by CAN or Ethernet controllers) would be the key for high throughput, I think.

Hi,
What about HP`s G(bit)-Link pls?
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=467775
Low Cost Gigabit Rate (High-Speed Serial Rate 150..1500MBaud) Transmit/Receive Chip Set with TTL I/Os:
http://www.datasheetcatalog.org/datasheet/hp/HDMP-1024.pdf
Its practically RT, has only a couple of bits header & Clk is transported as embebdded...
CAN or Ethernet are surly complexer to control & to end slower...
K.

With a bus architecture, address decoding and data filtering in the hardware interface (as performed e.g. by CAN or Ethernet controllers) would be the key for high throughput, I think.

Click to expand...

CAN is slower than i got and Ethernet works with packages... i cant have a fixed package .. i need to send several small messages.. 3 - 32 bytes. I could use FPGA at every network node but the problem is that this device is going to be used by people with low tecnical experience. The ideal of the system is to be flexible so if some one want to create a sensor node with a different sensor, it wont require lot of tecnical experience. FPGAs are more advanced than i expect users to deal with. The master of the Network is going to be a FPGA but i am going to design it and hopefully no one will ever have to touch on that. There is an IC from Cypress called HotLink II that would be very useful but it cost 100 USD each piece. Too expensive.

Hi,
What about HP`s G(bit)-Link pls?
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=467775
Low Cost Gigabit Rate (High-Speed Serial Rate 150..1500MBaud) Transmit/Receive Chip Set with TTL I/Os:
http://www.datasheetcatalog.org/datasheet/hp/HDMP-1024.pdf
Its practically RT, has only a couple of bits header & Clk is transported as embebdded...
CAN or Ethernet are surly complexer to control & to end slower...
K.

Click to expand...

Interesting, i could not find the IC on DIgiKey, farnell or Mouser... ANy idea where i can find it? The only problem is that the minimum speed is 150Mbps .. thats too high..

Added after 4 hours 51 minutes:

Got an Idea.. Please sugestions if it might work or not. At each comunication node i can use a LVTTL to LVDS serializer and deserializer conected to IDT5V5216 ( http://www.idt.com/?partId=5V5216PGGI ). The pararell inputs and outputs from de Serializer and Deserizlizerr I am going to conect to uCU or DSP. WIth that coniguration is going to be like:

LVTTL -> LVDS -> M-LVDS -> LVDS -> LVTTL

I could use PIC32 PMP as an axample to input paralel data on Serializer and read from Deserizalizer.. i am prety sure i can get something like PMP on other divices ...

Any sugestion?

Sink0 said:

... There is an IC from Cypress called HotLink II that would be very useful but it cost 100 USD each piece. Too expensive.

Hi,
...Low Cost Gigabit Rate (High-Speed Serial Rate 150..1500MBaud) Transmit/Receive Chip Set with TTL I/Os:
http://www.datasheetcatalog.org/datasheet/hp/HDMP-1024.pdf ...
K.

Click to expand...

Interesting, i could not find the IC on DIgiKey, farnell or Mouser... ANy idea where i can find it? The only problem is that the minimum speed is 150Mbps .. thats too high..

Click to expand...

Hali,
Eventually you can implement the "HotLink II " (like) protocol in an FPGA?_it can be cheaper as the HighTech IC...
HP (Agilent) ICs are to find by HP (& such special distributors as in EU_i.e. "EBV" ...
Btw; its possibly no more in program, I remember, that some years ago aI have read over a newer version, think is called: HDMP1032?...
K.

I doubt, that the said HotLink chips are still active parts at Avagotech.

When interfacing this chip or other SERDES solution to a uP, you'll face the problem, that transmitted data for any receiver
have to be processed and decoded by each of them to filter the dedicated data. This reduces the data rate of the serial bus
to the throughput of a single receiver. I can't imagine, that you get much more than 20 MBPS with general uPs.

Filteríng the data in the interface before delivering them to the uP increases the total data rate by a factor of n (number of
connected slaves), assuming that the uP data processing is the limiting factor.

Although involving considerable frame overhead, even ethernet (raw IP or UDP) would possibly perform better. I also don't
actually understand, why a "user" would have to deal with the design details of a FPGA based interface as long as he's using
a predefined protocol scheme. The application dependant part can be still handled by a uP.

Hali Sink0,
Check it pls by octopart; XSMicro has the old 1022/1024 too...
**broken link removed**
https://pdf1.alldatasheet.com/datasheet-pdf/view/113223/HP/HDMP-1032.html
K.

Hali Sink0,
Check it pls by octopart; XSMicro has the old 1022/1024 too...
**broken link removed**
https://pdf1.alldatasheet.com/datasheet-pdf/view/113223/HP/HDMP-1032.html
K.

Click to expand...

Thank you for the information.. i am going to take a quote to see how much that IC cost.

I also don't
actually understand, why a "user" would have to deal with the design details of a FPGA based interface as long as he's using
a predefined protocol scheme. The application dependant part can be still handled by a uP.

Click to expand...

People that are going to use this system are scientists and not engineer so luckly they going to have some one at their group that know how to use a 8-bit MCU. If they have to use the system with a diferent sensor than already implemented, i want it to be easy to be done (if they find out that they need to even understand what is a FPGA they going to give up, belive me). But i guess i wont be able to keep it simple and fast with one comunication tipe, i think i am going to leave both comunications available on the same CAT5 cable, RS485 and M-LVDS as i just need to use 1 pair for each. For M-LVDS i am using FPGAs and for handling all the communication and to have a FIFO. Probably for the nodes i am using the smallest FPGA possible (EP1C3) with 100 pins. What do you think about my solution? Will it work to use a small FPGA to handle all the communication?

I got some questions about using LVDS ports on FPGA but i will create a thread at FPGA forum.

Thank you for everything so far.

Hi Sink,
I have read these solution yet; maybe is some thing for your problem too?
XAPP1064 - Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s)
https://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf
K.