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vhdl synthesizable codes for fast adders and fast multiplier

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MOOMOO_KAMP81

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can anyone help me in finding synthesizable codes for fast adders and fast multiplier? ,i need them for using in a convolution function.
 

Re: vhdl synthesizable codes for fast adders and fast multip

I dont know about adders.I think the xilinx will implement the fastest adders during synthesis.
You can choose the optimization method by changing the synthesis option in XST.
Change the "optimization goal" to "speed" in XST synthesis options.

And for the multiplier you can increase the speed by using cris-cross way of multiplication, found in Vedic Mathematics. It will increase the operating freq by a good amount.

Hope this helps.
--vipin
https://vhdlguru.blogspot.com/
 

Synthesisors are good at implementing multipliers and adders from the following code. I assume you're talking about synchronous adders/multiplers rather than asynchronous.

signal a,b,c,d : integer range LOW_LIMIT to HIGH_LIMIT;

--inside a clocked process;
c <= a + b;
d <= c * a;
 

Re: vhdl synthesizable codes for fast adders and fast multip

my code should not be behavioral specifically for + ,so i should find some code for implementing fast adder
 

Re: vhdl synthesizable codes for fast adders and fast multip

I think, the question title is misleading. This is no VHDL problem. You have to refer to the low level hardware primitives of the respective FPGA family. The vendor usually has examples how to utilize them in a VHDL design, like the Altera "Synthesis Cookbook".

But in most the cases, the synthesis tool can be expected to generate almost optimal gate level logic from behavioural code, as already mentioned.
 

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