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How to make an array in verilog equal zero ?

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eng_msa_8_8

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hi to all
i have an array in verilog code
Code: 
  reg [7:0] memory [15:0];

how can i make it equal zero ???
 

array in verilog ?

for (i=0; i<16; i=i+1)
begin
reg = 8'h00;
end
 

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