What is a stable clock and how to generate it in Xilinx ISE?

what is stable clock and how can we generate the stable clock using DCM in xilinx ise?

stable clock

a stable clock is a clock where each period takes the same amount of time.

this means, as example, a 100MHz clock has a rising edge every 10ns.

this is different than having a rising edge every 1ns for 10 edges, then waiting 90ns. (bursty clock)

it is also different than having a clock after 9ns, then 11ns, then 8ns, then 10ns, then 12ns, then ... (high jitter clock)


a DCM is a form of delay-locked loop. The way to use it is fully described in the user guide. It can be used to generate a "zero-delay buffer", as well as uses for frequency synthesis. Advanced uses for fine phase-shifting are also possible. The ISE "library for HDL" has examples for DCM_BASE and DCM_ADV.

keep in mind that the "locked" indicator for the DCM is a bit unreliable. If "locked" is 0, then the clock is not stable. if "locked" is 1, the clock might be stable. unfortunantly, one use case of DLL's prevents the DCM "locked" signal from being useful in the ZDB/freq-synth case.

(a DCM is higher jitter than the V5's PLL. connecting a DCM output to another DCM input will eventually lead to a clock that never "locks". DCMs also have 2 frequency ranges, low/high. this sets an upper/lower bound on the input frequency. for frequency synthesis, there are additional limits.)

Re: stable clock

Thanks for your reply