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Concern of connecting thin-oxide device to ground/power

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neoflash

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In sub-130nm process, tsmc requested to use tie-high tie-low for soft connection to power/gnd bus.

Not sure what kind of issue is getting worried? CDM, HBM, or CMP during manufacturing?
 

Neither of those, because models aren't dangerous from themselves, and CMP occurs under an electrolytically conducting liquid. It's simply a better gate protection during a "normal" ESD event, than connecting directly to GND or VDD.
 

I am suspicious of the simple "tie_x" cells because they just
substitute one gate-big rail connection for another. Seems to
me like "feel-good" without backup.

On the plus side verilog will have a model for it, unlike a resistor
of equivalent drive strength.

On the other hand I have cheated the antenna rules more than
once, by using a resistor to tie gates to vdd/vss.
 

i think never let the gate of a not used transistor floating is a good habit.
and the floating gate is potentially threatened by antenna effects and CDM events. gate means capacitances, charges love capacitors, electro-static charges will be stored there.
 

This is a good question. Made me think.

If we put a tie-low, now the nmos of tie low is connected directly to ground so if it was an ESD zap protection thing, won't the inverter nmos get blown up.
 

I dug around somewhat. It seems that we use tie-low because you don't want to connect directly to Vcc. so you create a softvcc.

However, we don't use a tie-high. Its okay to connect a gate directly to ground.
 

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