Help me with working with VHDL text I/O to read data

vhdl function to parse text file

Hi :

I'm working with VHDL text I/O to read data from text files and to write the output back into a text file. The input file is a text file and it has data in the form of a matrix (integer values). Basically the text file has image data. I need to read this data in matrix form. To do that I defined an array and called a function to return an after reading all the values from the text file. But it is not working that way. So, I would appreciate if somebody can give me an idea regarding the same.

Thanks,
MS

vhdl read file into an array

paste you code here. i think it will be possible to find where you are making mistake

Re: VHDL Question

Hi Shiva:

Thanks for the reply. Here is the code I used for reading values from file into an array. This process is similar to an example from Designer's guide to VHDL (By Peter Ashenden). I'm not sure as to where the problem is.Please help me out with this.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.data.all;

entity PE is
port (search_data1_in : in data_array;
current_data1_in : in data_array;
clk,reset : in std_logic;
);
end PE ;

architecture BEHAVE of PE is
signal search_data_in,search_data1_in1 : data_array;
signal current_data1_in1,current_data_in : data_array;

type integer_file is file of integer;
file data_in : integer_file is in "sample.txt";

component S_DRAM
port(s_address : in std_logic_vector(15 downto 0);
clk,reset : in std_logic;
s_we : in std_logic;
s_ras,s_cas : in std_logic;
s_row,s_col : out integer;
search_data_in : in data_array;
search_data_out : out data_array
);
end component;

begin

DRAM_S : S_DRAM port map(s_address => s_address, clk => clk, reset => reset, s_we => s_we, s_ras => s_ras, s_cas => s_cas, s_row => s_row, s_col => s_col, search_data_in => search_data_in, search_data_out => search_data1_in1);


process

type Y_array is array (1 to 2,1 to 2) of integer;
variable Y : Y_array;
begin
while not endfile (data_in) loop
for i in 1 to 32 loop
for j in 1 to 32 loop
read(data_in,Y(i,j));
end loop;
end loop;
end loop;
wait for 2 ns;
end process;

end behave;

Also, I need to divide this matrix (say 32x32) to blocks of size 2x2. I'm not sure where to start on this.I would really appreciate,if you can give some suggestions in implementing this.

Thanks,
MS

VHDL Question

your variable Y is only 2x2, so you cannot assign 32x32 to it.
you may make new type is 16x16 of Y_array, so size of this new type will be same as 32x32.

Re: VHDL Question

modukuri said:

Hi Shiva:

Thanks for the reply. Here is the code I used for reading values from file into an array. This process is similar to an example from Designer's guide to VHDL (By Peter Ashenden). I'm not sure as to where the problem is.Please help me out with this.

process

type Y_array is array (1 to 2,1 to 2) of integer;
variable Y : Y_array;
begin
while not endfile (data_in) loop
for i in 1 to 32 loop
for j in 1 to 32 loop
read(data_in,Y(i,j));
end loop;
end loop;
end loop;
wait for 2 ns;
end process;

end behave;

Thanks,
MS

Click to expand...

What you're doing is binary file I/O by declaring the file as a file of integer. Now you're reading the file 4 bytes (or so, simulator dependant!) at a time and storing the byte values as an integer. What you wanted was text-based I/O, I believe.
So you need to use the textio package, declare the file as type "text", read a line of this text using readline(), and then parse the line one number at a time with read().

Re: VHDL Question

Hi :

I already tried using textio to read the data,but it still didn't work. Also, I have the data values seperated by a space(i.e., the delimiter for the file is a "space").How can I include that in the process to read the delimiter after every value.Here is what I did using textio.

library IEEE;
use IEEE.std_logic_1164.all;
use numeric_std.all;
use IEEE.std_logic_unsigned.all;
std.textio;

file data_in : text is in "sample.txt";

type data_array is array(1 to 32,1 to 32) of std_logic_vectro(7 downto 0);
signal data1 :data_array;

process

type Y_array is array (1 to 32,1 to 32) of integer;
type un_array is array (1 to 32,1 to 32) of unsigned(7 downto 0);
variable Y : Y_array;
variable Y_un : un_array;
variable inline : line;
begin
for i in 1 to 32 loop
for j in 1 to 32 loop
while not endfile (data_in) loop
readline(data_in,inline));
read(inline,Y(i,j));
Y_un(i,j) := to_unsigned(Y(i,j),8);
data1(i,j) <= std_logic_vector(Y_un(i,j));
end loop;
end loop;
end loop;
wait for 2 ns;
end process;

I'm not sure as to why the values are not read from the file.Please I need some help in solving this.

Thanks,
Modukuri

Re: VHDL Question

Strange: if you code the loop like

then you will read item i=1, j=1 and parse the entire file (while not endfile) for that one item. Are you sure about the while loop?

Also, if you do a readline, you consume an entire line, but I guess you only want to do that for every i, not every j iteration?

Is this more like what you want?

If this doesn't help, please show the contents of the .txt file you try to parse. I assume it is like
right?[/quote]

One more thing: a process without sensitivity list restarts after it reaches "end process" so you will probably want to replace the wait 2 ns; by an infinite wait;. You don't want to restart the process after the 2ns I presume?

Re: VHDL Question

need same requirment but the , my code is ok , i use altera v7 , but no out file update,

or

is textio supported in altera ???????????????????