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2nd July 2010, 21:16 #1
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DSP: cascaded integrated comb filters
I'm trying to work out the output states for each stage of a CIC, and I'm a bit confused.
If an integrator looks like this:
And it's output is described as
Code:S1[n] = S1[n1] + X1[n]
Code:S2[n] = S2[n1] + X2[n]
Code:S2[n] = S2[n1] + S1[n1] + X1[n]
The implementation I am analyzing does not do that, and has a register for each accumulator stage, therefore the input does not propagate. Is this correct? What am I missing?

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3rd July 2010, 16:29 #2
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DSP: cascaded integrated comb filters
Usually, you'll want to utilize the delay register to achieve pipeline action and connect the next stage at it's output rather than at the adder directly.
A separate pipeline register may be used, if the CIC integrator clock is as divided system clock.

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6th July 2010, 09:47 #3
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Re: DSP: cascaded integrated comb filters
Originally Posted by casey480
Code:S1[n] = S1[n1] + X1[n] S1[n1] = S1[n2] + X1[n1] S1[n] = S1[n1] + X1[n] = S1[n2] + X1[n1] + X[n]

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6th July 2010, 09:59 #4
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Re: DSP: cascaded integrated comb filters
the final equation is wrong

6th July 2010, 12:32 #5
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Re: DSP: cascaded integrated comb filters
Originally Posted by FvM
Code:S1[n] = S1[n1] + X1[n] = S1[n] * (z ^ 1) + X1[n]; S1[n](1  (z ^ 1)) = X1[n] H(z) = S1[n]/X1[n] = 1/(1  (z ^ 1));
Code:F(z) = H(z) * H(z) = 1/(1  2 * (z ^ 1) + (z ^ 2)) = S2[n]/X1[n]
Code:X1[n] = S2[n] * (1  2 * (z ^ 1) + (z ^ 2)) = S2[n]  2 * S2[n1] + S2[n2];
Code:S2[n] = 2 * S2[n1]  S2[n2] + X1[n];
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