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Is sign off LVS check neccessary for Encounter based PnR

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Greatrebel

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Hi All,

I would like to ask whether sign off LVS by tools like Assura and Calibre is really neccessary for Encounter based PnR. Because the layout and schematic are all from the layout generated by Encounter. I think ideally they should be same, not like the custom layout design where the schematic and layout are generated seperately by different engineers. And also Encounter does have some basic connectivity check, sign off LVS seems like not that important. Am I right?



Thank you very much
 

In my flow LVS and DRC using Calibre or similar tools are always required, no matter what other tools are used in the flow. That's because Encounter and other layout tools work with LEF abstractions, not the actual GDS2 which is used to make the masks. It's possible to have a mismatch between LEF and GDS2, and SOCE would never find it. Also, at least in my case, there are usually special structures in the IO region and corner cells that SOCE doesn't understand or know how to check. If you had the wrong corner cell, or missing a cut buffer or something, you'd never know without true LVS.
 

Hi randyest,

Thank you very much for your reply. My case is that I can not get the layout details for std cell, memory block, IO and so on from the foundry. All what I have are LEF files, and the gds I export from Encounter does not have the detailed layout information for those blocks. So I am wondering whether it is still neccessary to do sign off LVS in this case.
 

By "layout details" I guess you mean spice/primspice files needed to create a layout netlist? I guess you can't really do LVS without that info, but I would still be worried and ask the Foundry for help or explanation why they can't provide data needed for LVS.

What do they say when you ask? Maybe they expect to do LVS for you?
 

The foundry does not allow us to see the layout of std cells for the confidential reason. So we do not have the spice file and gds file for std cell, memory blocks and IOs. But they do not do sign off LVS for us, they said "we are able to perform LVS with the phantom views of the standard cells".

thanks a lot
 

So you have LEF, but not GDS2 or primspice? I've never used LEF for LVS in Calibre, but if your foundry says it's possible maybe they can give you some hints, or maybe your Calibre support? Sorry I can't be of more assistance.
 

It is possible to do LVS even if you do not have the gds/spice info of the standard cells. This is done by labeling all the cells as blackbox in calibre or assura.
 

hi wpchan05，

I am just wondering whether it is still useful to do LVS without spice and gds for std cells, because both layout and schematic are from Encounter. Ideally they should match, if there is not any full layout gds lib merged into the design, right?
 

I think it is a good practice to do LVS whenever you made change in the layout, no matter it is from Encounter or Virtuoso XL. Doing the LVS won't take us a long time, and it gives us confidence that the updated layout is corresponding to the schematic.
 

Hi wpchan,

When I use Calibre to check LVS, I got a lot of errors like


Error: No matching ".SUBCKT" statement for "PRUW1216SCDG_25" at line 12745 in file "/home/hanwei/workspace/MAC/signoff/calibre/_ptmac_post_layout_calibrein.v.sp"

Error: No matching ".SUBCKT" statement for "BUF" at line 575 in file "/home/hanwei/workspace/MAC/signoff/calibre/_ptmac_post_layout_calibrein.v.sp"

Error: No matching ".SUBCKT" statement for "NOT" at line 819 in file "/home/hanwei/workspace/MAC/signoff/calibre/_ptmac_post_layout_calibrein.v.sp"

But I have alread included all the verilog library into the input netlist. I do not know why I still got so many reference errors. Could you please give me a help on it.

Thank you very much
 

Those errors are referring to missing spice netlists. You can't use verilog models in place of spice netlists.
 

Greatrebel said:
Hi wpchan,

When I use Calibre to check LVS, I got a lot of errors like


Error: No matching ".SUBCKT" statement for "PRUW1216SCDG_25" at line 12745 in file "/home/hanwei/workspace/MAC/signoff/calibre/_ptmac_post_layout_calibrein.v.sp"

Error: No matching ".SUBCKT" statement for "BUF" at line 575 in file "/home/hanwei/workspace/MAC/signoff/calibre/_ptmac_post_layout_calibrein.v.sp"

Error: No matching ".SUBCKT" statement for "NOT" at line 819 in file "/home/hanwei/workspace/MAC/signoff/calibre/_ptmac_post_layout_calibrein.v.sp"

But I have alread included all the verilog library into the input netlist. I do not know why I still got so many reference errors. Could you please give me a help on it.

Thank you very much
Click to expand...

The attached pdf might give you some hints on how to do LVS in blackbox approach (However, the content of the pdf is in chinese, but you might spot the flow if you are careful)
 

Hi wpchan,

Thank you very much for the document. The document is saying for black boxes, using LVS BOX Block_name in the LVS command fie. But for my case, it is still not working. Do you have any further suggestion.

Hi randyest,

For spice netlist, can I use verilog netlist to generate it or I have to get it from the foundry?

Thank both of you
 

Greatrebel said:
Hi wpchan,
Hi randyest,

For spice netlist, can I use verilog netlist to generate it or I have to get it from the foundry?

Thank both of you
Click to expand...
You need verilog netlist and the primspice netlists (SPICE cubcircuits for all the primitives and macros in your design.)
 

wpchan05 said:
It is possible to do LVS even if you do not have the gds/spice info of the standard cells. This is done by labeling all the cells as blackbox in calibre or assura.
Click to expand...

hi
i have the same problem with calibre ....
i've used the LVS BOX statement
but same errors and wornings
i've the gds out of the encounter
and the verilog file also out of the encounter

the calibre v2lvs translates my verilog into spice using the verilog libraries..
the source netlist in verilog is correctly translated into spice.

i don't have spice libraries ... only verilog libraries ! why they are not sufficient ?

the extracted layout netlist is just an empty subcircuit !!! where all the cells are gone ?
can anybody help me ?
 

pervanah said:
i don't have spice libraries ... only verilog libraries ! why they are not sufficient ?
can anybody help me ?
Click to expand...

Perhaps you can create a spice library of the standard cells. The spice description in the library is just the name of the cells plus their ports instantiations.

pervanah said:
the extracted layout netlist is just an empty subcircuit !!! where all the cells are gone ?
can anybody help me ?
Click to expand...

If you do not have the lef of the standard cells, the extracted layout netlist should only has the cells and nets. You will not get any transistor information out from Encounter.
 

wpchan05 said:
It is possible to do LVS even if you do not have the gds/spice info of the standard cells. This is done by labeling all the cells as blackbox in calibre or assura.
Click to expand...

yes by LVS BOX statement in calibre , but it just doesn't work ( i don't know why) , the extracted netlist from layout ignores the cells stated as black boxes !! an incomplete extracted netlist and useless LVS :( !!!

Added after 5 minutes:

wpchan05 said:
If you do not have the lef of the standard cells, the extracted layout netlist should only has the cells and nets. You will not get any transistor information out from Encounter.
Click to expand...

hi :)
thx for your answer ... but in the encounter , the lef files ( technology files ) of the standard cells are all in , input when creating the layout .
although that fact , the gds out of the encounter is just the cells as black boxes and the nets .. i use the tsmc90nm kit ..
 

wpchan05 said:
If you do not have the lef of the standard cells, the extracted layout netlist should only has the cells and nets. You will not get any transistor information out from Encounter.
Click to expand...

hi :)
thx for your answer ... but in the encounter , the lef files ( technology files ) of the standard cells are all in , input when creating the layout .
although that fact , the gds out of the encounter is just the cells as black boxes and the nets .. i use the tsmc90nm kit ..[/quote]

My bad. I should say if you do not have the gds file of your standard cells, you will never get transistor infomration out from Enocunter.

You need to check whether your pdk is a taped out kit or design kit. A taped out kit gives you all the transistor information about the standard cells in terms of schematics, model files, and layouts. A design kit only gives you only a verilog/timing/lef of the standard cells.
 

your LVS will only check the correct connection from pin to pin, the founder will garantue the correct std cell LEF model, and I expect the founder also run a LVS on our design!!
 

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