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Understanding of LVDS protocol

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Meach_bzh

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Hello,

I would like to do a LVDS to RGB converter in a FPGA but I have difficulties to understand how is encoded the LVDS signal.
I especially want to know the number of channel and deserialization factor I should use in my converter.

the LVDS transmitter used to generate the LVDS signal is:
**broken link removed**

The LVDS pins I have are:
A0_P
A0_N
A1_P
A1_N
A2_P
A2_N
A3_P
A3_N
AC_P
AC_N
DDC_CLK
DDC_DAT
VDD_EN
BKLT_EN
BKLT_CTRL

Should I assume that I have 4 channels? If yes, how can I find the deserialization factor I should use? I have a logic analyser and maybe thought that I can look at the clock pins (AC_N & AC_P???).

If you have ideas and information I would glad to hear them.

Cheers
 

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