supercat
Member level 3
In CPLD designs which have extra I/O's but are short on registers, has anyone used I/O's configured as "bus hold" as extra logic (using "output enable" as a latch-enable signal)? Are there any particular limitations?
I would expect that because enabling output will turn on strong transistors, that such pins should switch quickly. If the pins are open-circuit, then absent external disturbance, they should reliably remain switched. A metastable state could arise if the output enable was pulsed too briefly, but without any external capacitance the pins should switch thoroughly for all but the shortest enable pulses.
I'm presently using a Lattice 4064ZE in a 44-pin package. Ideally, I could use non-bonded pins for registers; does anyone know of any "nice" way to do that in the fitter? The only approach I can see is to lie to the fitter, say I'm using a 100-pin part, and then remap all my pin numbers, but that seems icky. Are there any better ways?
Also, the data sheet shows an output routing pool between the macrocells and the I/O pads. If two I/O pins share the same logic equations, and both are within "routing distance" of one macrocell, is there any way to convince the fitter to map that macrocell to both pads? If so, one could add small amounts of RAM or grayscale counters to a design using very few macrocells.
I would expect that because enabling output will turn on strong transistors, that such pins should switch quickly. If the pins are open-circuit, then absent external disturbance, they should reliably remain switched. A metastable state could arise if the output enable was pulsed too briefly, but without any external capacitance the pins should switch thoroughly for all but the shortest enable pulses.
I'm presently using a Lattice 4064ZE in a 44-pin package. Ideally, I could use non-bonded pins for registers; does anyone know of any "nice" way to do that in the fitter? The only approach I can see is to lie to the fitter, say I'm using a 100-pin part, and then remap all my pin numbers, but that seems icky. Are there any better ways?
Also, the data sheet shows an output routing pool between the macrocells and the I/O pads. If two I/O pins share the same logic equations, and both are within "routing distance" of one macrocell, is there any way to convince the fitter to map that macrocell to both pads? If so, one could add small amounts of RAM or grayscale counters to a design using very few macrocells.
