reading image data stored in text file using vhdl in xilinx

Re: reading image data stored in text file using vhdl in xil

hi guys the same i have do it in verilog....can someone help me out...

Re: reading image data stored in text file using vhdl in xil

hii i am trying to simulate this code in modelsim ,but it is giving me the error

# ** Fatal: (vsim-3551) TEXTIO : Read past end of file "stennis1.txt".
# Time: 0 ps Iteration: 0 Process: /image_read/recievedata File: C:/Users/KAKARALA/Desktop/image_read.vhd
# Fatal error in ForLoop loop at C:/Users/KAKARALA/Desktop/image_read.vhd line 55

can anyone pls help me?


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity image_read is

--port(
--type img_array_t is array(natural range <>, natural range <>) of natural;
--signal img_array : img_array_t(0 to 239, 0 to 351));

end image_read;

architecture Behavioral of image_read is

type img_array_t is array(natural range <>, natural range <>) of natural;
signal img_array : img_array_t(0 to 239, 0 to 351);

begin

recievedata: process
--variable img_array : img_array_t(0 to 239, 0 to 351);
file img_file : text open read_mode is "stennis1.txt";
variable l : line;
variable temp : natural;

begin
for y in 0 to 351 loop
readline(img_file,l); --gets 1 line at a time
for x in 0 to 239 loop
read(l,temp); --read in each pixel
img_array(x,y) <= temp;
end loop;
end loop;
wait;
end process;

end Behavioral;

Id have thought the error was self explanitory. You're trying to read past the end of the file.

The for loop that uses the "y" variable loops too many times!

Re: reading image data stored in text file using vhdl in xil

yes but size of image in the text file is 240 * 352, i need to create array of size 240 *352 .

you have y and x mixed up.

there are only 240 lines in the image, and you're trying to read 352.

Change it to:

hi ,
how to create text file of an image pls tell me i`m new to vhdl coding pls pls i`m in need of it.
pls mail me at chitraranganath@gmail.com

hi
can anyone give the test bench code of reading the image text file for simulation of the main file???

There are plenty of textio tutorials out there - use google.

thnku
i tried a lot but they are not working???

Ive never had a problem. Why not post what problems you're having as the telepathic part of my brain isnt working today.

mohassin said:

i tried a lot but they are not working???

Click to expand...

So list what you tried and failed with. What tutorial did you use, and what code did you produce?

thnku for your response

Below is the code for convolution ppeline I have used the component approach .I want to give image data as the input and process it .Is there any way ??
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity conv3 is
port( data : in STD_LOGIC_vector(71 downto 0);
clk1,rstn1: in std_logic;
dout : out STD_LOGIC_vector(15 downto 0));
end conv3;
architecture Behavioral of conv3 is
component aaa is
port(l,m,n :in std_logic_vector(7 downto 0);
p,q,r :in std_logic_vector(7 downto 0);
clk,rstn:in std_logic;
dout1ut std_logic_vector(15 downto 0));
end component;
component adder2 is
Port ( a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(15 downto 0);
c : in STD_LOGIC_VECTOR(15 downto 0);
d : out STD_LOGIC_VECTOR(15 downto 0));
end component;
constant k0 : std_logic_vector (7 downto 0):= "00000001";
constant k1 : std_logic_vector (7 downto 0):= "00000010";
constant k2 : std_logic_vector (7 downto 0):= "00000001";
constant k3 : std_logic_vector (7 downto 0):= "00000010";
constant k4 : std_logic_vector (7 downto 0):= "00000100";
constant k5 : std_logic_vector (7 downto 0):= "00000010";
constant k6 : std_logic_vector (7 downto 0):= "00000001";
constant k7 : std_logic_vector (7 downto 0):= "00000010";
constant k8 : std_logic_vector (7 downto 0):= "00000001";
signal a1,a2,a3,a4:std_logic_vector(15 downto 0);
begin
u1:aaa port map(data(71 downto 64),data(63 downto 56),data(55 downto 48),k0,k1,k2,clk1,rstn1,a1);
u2:aaa port map(data(47 downto 40),data(39 downto 32),data(31 downto 24),k3,k4,k5,clk1,rstn1,a2);
u3:aaa port map(data(23 downto 16),data(15 downto 8),data(7 downto 0),k6,k7,k8,clk1,rstn1,a3);
u4:adder2 port map(a1,a2,a3,a4);
dout <= a4;
end Behavioral;




i tried to read text file in test bench by a process. Apart of that code is below
------------------------------------------------------
file img_file : text open read_mode is "stennis1.txt";
variable l : line;
variable temp : natural;

begin


for y in 0 to 127 loop

readline(img_file, l); --gets 1 line at a time

for x in 0 to 127 loop
read(l,temp); --read in each pixel
img_array(x,y) <= temp;
end loop;
end loop;

end process;

-----------------------------------------------
now can u help me out of this plzz???

but you didnt say what the problem is. The code looks like perfectly good code, apart from the fact there is no wait statement at the end, so it will try and loop through the process forever (and because you went off the end of the file in the first time through, it'll bomb out on the 2nd time through with past end of file error.

Thnku sir
i have the problem that how to feed image data as input ?? For that i
convertd the image into a text file but i do not know how to use it as
the input so that my data is read from text file ?? Help me for this
plz

you have the img_array signal - isnt that an input to your design?

i have declared img_array signal only in test bench so that i could read the image data
I have teshbench code below
------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_textio.all;

USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;

library STD;
use STD.textio.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY c_tbw IS
END c_tbw;

ARCHITECTURE behavior OF c_tbw IS
--type img_array_t is array(0 to 127,0 to 127) of natural;
--signal img_array: img_array_t;

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT conv3
PORT(
data : IN std_logic_vector(71 downto 0);
clk1 : IN std_logic;
rstn1: IN std_logic;
dout : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;

--Inputs
signal data : std_logic_vector(71 downto 0) := (others => '0');
signal clk1 : std_logic := '0';
signal rstn1 : std_logic := '0';

--Outputs
signal dout : std_logic_vector(15 downto 0);


-- Clock period definitions
constant clk1_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: conv3 PORT MAP (
data => data,
clk1 => clk1,
rstn1 => rstn1,
dout => dout
);

-- Clock process definitions
clk1_process rocess
begin
clk1 <= '0';
wait for clk1_period/2;
clk1 <= '1';
wait for clk1_period/2;
end process;

lecturarocess
variable rdline : line;
variable a_tmp : std_logic_vector(71 downto 0);
file vector_file : text open read_mode is "C:\Users\user\Desktop\text.txt";
begin
while not endfile(vector_file) loop
readline(vector_file, rdline);
read(rdline, a_tmp);
data <= a_tmp;
wait for 1 ns;
end loop;
wait;
end process;
END;
------------------------------------------------------------------------------------
but this shows me error
Error: READ(STD_ULOGIC_VECTOR) Error: Character '4' read, expected STD_ULOGIC literal.



can u please help me ???

It sounds like you have decimal values in the file. But read(l, slv) expects binary format in the file. you can also use oread(l, slv) for octal format, or hread(l, slv) for hex format, but you cannot read decimal format into a std_logic_vector. for decimal you need to read it into an integer and then convert it to a std_logic_vector.

- - - Updated - - -

PS. If you had told us this yesterday you wouldnt have had to wait so long for an answer!

- - - Updated - - -

Another point to note - you have used numeric_std and std_logic_arith packages in the same file - you shouldnt do this as they cause conflicts. Anticipating your next question of "How do I read an integer" you should first remove the std_logic_arith package as it is non standard anyway.

thanks for your response sir


I have already converted the image matrix in binary using matlab.
now i have also removed std_logic_arith package but there is still the same error
Error: READ(STD_ULOGIC_VECTOR) Error: Character ',' read, expected STD_ULOGIC literal.

you clearly have illegal characters in your text file. You need to review the contents.

- - - Updated - - -

when reading text, the only legal characters for std_ulogic are '1', '0', 'X', 'U', 'W', 'L', 'H', '-' and 'Z'

the text file that i used is attached below.I can not understand where is the fault . So please can u check this file ??? what needs to done ???