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Biasing common source output stage

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jszair

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In typical two-stage opamp, second stage is usually a common source gain stage with current mirror load, like in miller opamp. How to actually bias this stage? Since it is essentially an inverter, the dc operating point of output node is very unstable and either nmos or pmos could easily goes into linear region and kill the gain...

any suggestion on biasing common source stage?
 

Tailor the current mirror for the required output current, then dimension the nMOS W/L for VDD/2 quiescent output voltage at typ. cond. Correct feedback should approximately keep the output voltage at this level. See e.g. the PDF below.
 

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