Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to remove the glitches

Status
Not open for further replies.

prcken

Advanced Member level 1
Joined
Nov 1, 2006
Messages
419
Helped
41
Reputation
82
Reaction score
37
Trophy points
1,308
Location
Shanghai
Activity points
4,059
hello all
i attached a circuit schematic and its simulation waveform, could you tell me how to remove the glitches in terms of this circuit?
really appreciate!
-Kehan
 

dick_freebird said:
I do not notice any glitches in the waveform plots.

you are right, i am sorry for putting a wrong picture there.
i will change it tomorrow.
thanks for your reminding.
 

dick_freebird said:
I do not notice any glitches in the waveform plots.

hello dick_freebird
i have updated the waveform, as you can see, there is a glitch at the rising edge, i trimmed the load resistors found that smaller resistance would make the case even more worse.
but to my understanding, the smaller resistance, the smaller τ, the faster charging will be.
what's more, the divider works at lower frequency, similar glitches at the falling edge will also be observed. any comments?
thanks
-Kehan
 

I think that is the Miller capacitance, pushing back on a weak
gate discharge. Perhaps you want more tail current. Or
perhaps less finger count in the switching pairs. Current
density tends to maximize speed. That CML gate is basically
a tall cascode amplifier, high impedance at the drain.
High Z tends to lower bandwidth. To that end, have you
played with shortening the bias devices? Lower Zout might
"up the bandwidth" at the upper gates.
 

dick_freebird said:
I think that is the Miller capacitance, pushing back on a weak
gate discharge. Perhaps you want more tail current. Or
perhaps less finger count in the switching pairs. Current
density tends to maximize speed. That CML gate is basically
a tall cascode amplifier, high impedance at the drain.
High Z tends to lower bandwidth. To that end, have you
played with shortening the bias devices? Lower Zout might
"up the bandwidth" at the upper gates.

i can not short the bias device, this divider need the bias to supply tail current.
what's more, it seems that the divider is getting worse at relatively lower frequencies.
the attached waveforms are output at 450MHz, when the input is 900MHz, the waveform is too ugly.
 

To me it looks like the result of parasitic oscillations within the circuit.
To check it, remove the input and terminate the input by the proper source impedance.
 

LvW said:
To me it looks like the result of parasitic oscillations within the circuit.
To check it, remove the input and terminate the input by the proper source impedance.

you meant try to tie the input through a proper resistor to ground?
the waveform of the inputs seems ok, this the input waveforms after the AC capacitance.
 

prcken said:
LvW said:
To me it looks like the result of parasitic oscillations within the circuit.
To check it, remove the input and terminate the input by the proper source impedance.

you meant try to tie the input through a proper resistor to ground?
the waveform of the inputs seems ok, this the input waveforms after the AC capacitance.

Yes, but without any input signal you can see if there are parasitic oscillations!
 

LvW said:
prcken said:
LvW said:
To me it looks like the result of parasitic oscillations within the circuit.
To check it, remove the input and terminate the input by the proper source impedance.

you meant try to tie the input through a proper resistor to ground?
the waveform of the inputs seems ok, this the input waveforms after the AC capacitance.

Yes, but without any input signal you can see if there are parasitic oscillations!

hello, i increased the tail current from 300u to 580u, reduced load resistance from 2400ohm to 1600ohm, got the waveform in figure1. glitch still exists.
then set input signals to zero. got the output waveforms as shown in figure2.
in figure2, the waveform is very smooth, and the self-oscillation frequency is about 384MHz.

why outputs are deteriorated by looking good input waveforms? how do parasitics at the inputs play a role?

thanks
-Kehan
 

Hi prcken,
Sorry, but if Im right; your circuit oscillates inself, than these signal will interfer with your input or regular signal...
These is the effect of form changes too if your tested-simulated frequency are changed/lowered! :-(
Good progress!
K.
 

karesz said:
Hi prcken,
Sorry, but if Im right; your circuit oscillates inself, than these signal will interfer with your input or regular signal...
These is the effect of form changes too if your tested-simulated frequency are changed/lowered! :-(
Good progress!
K.

hello K
this circuit features both a latch phase and an amplifier phase is called CML DFF divider which can self-oscillate. this self-oscillation frequecny is called centre frequency, there is a minimun amplitude requiremnt of the input signal as the output frequency increases or decreases. the output freq. is divided by two compared with the input freq.
this kind of circuit can even work up to 10GHz, so the output waveform could be smooth and should be at relatively lower freq.
-Kehan
 

OK,
These function was new for me-tnx!
Other question, that a signal output has to be clean here too, but you knows it...
K.
 

karesz said:
OK,
These function was new for me-tnx!
Other question, that a signal output has to be clean here too, but you knows it...
K.

yes, signal output has to be clean.
i have a chain of dividers with buffers, the output of this stage is too bad even though i can smooth it followed by a buffer. it should be and can be clean at the very output, too.
but i couldn't tune it well for the time being, that's my problem here:)
 

prcken
What process is this in? You see the voltage is >1.1V.
Also can you post a schematic of the circuit. That will help.
 

love_analog said:
prcken
What process is this in? You see the voltage is >1.1V.
Also can you post a schematic of the circuit. That will help.

hi, this is in a 0.18um mixed-signal CMOS process. the simulation results i got is at 1.62V supply voltage.
i have already put the schematic (should download to see it) at the beginning of this topic.:)
-Kehan
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top