Multiple clocks syntheis in design compiler

Hi All ,

We have a digital block in which we use a divider internally to generated divided clocks.
There is logic between these divided clocks . We hard instantiated the divider flops to be able to clearly specify the generated clock pins .

However when I look at the timing on paths from clk1 to clk2 (where clk1, clk2 are generated clocks), the delays of the elements along the path are reported as zero ! Any idea on why this might be happening ? below , I've attached the results of a 'report timing ' command. We see the the clock to Q delay of the flop t1_0_reg_0 is reported as zero !! I've seen that for paths from clk1 to clk1, or for for paths from clk2 to clk2 this problem does not exist .

I though it might be a Design compiler version problem, but other versions also show the same behaviour . Any pointers would be very helpful

Thanks ,
Karthik

Startpoint: t1_0_reg_0_
(rising edge-triggered flip-flop clocked by clkby1)
Endpoint: t1_d0_reg_0_
(rising edge-triggered flip-flop clocked by clkby2)
Path Group: clkby2
Path Type: max

Des/Clust/Port Wire Load Model Library
------------------------------------------------
haar enG5K fsc0h_d_sc_wc

Point Incr Path
-----------------------------------------------------------
clock clkby1 (rise edge) 80000000.00
80000000.00
clock network delay (ideal) 0.00 80000000.00
t1_0_reg_0_/CK (QDFFRBEHD) 0.00 80000000.00 r
t1_0_reg_0_/Q (QDFFRBEHD) <- 0.00 80000000.00 f
U56/O (XNR2CHD) 0.00 80000000.00 r
t1_d0_reg_0_/D (QDFFRBEHD) 0.00 80000000.00 r
data arrival time 80000000.00

clock clkby2 (rise edge) 160000000.00
160000000.00
clock network delay (ideal) 0.00 160000000.00
clock uncertainty -0.20 160000000.00
t1_d0_reg_0_/CK (QDFFRBEHD) 0.00 160000000.00 r
library setup time -0.12 160000000.00
data required time 160000000.00
-----------------------------------------------------------
data required time 160000000.00
data arrival time -80000000.00
-----------------------------------------------------------
slack (MET) 80000000.00

Added after 1 hours 48 minutes:

Hi ,

We noticed that when we tried to synthesize the same design at a higher speed, this odd behaviour disappeared ! The cell delays were no longer being reported as zero !

Regards,
Karthik

HI jkarthikr:
I think you can ignore the problem, because the cell delay is so small ralated to the clock period.
what u puzzled is why timing calculator ignores the cell delay, please try to change the variable value :report_default_significant_digits, the default vaule is 2
good luck!

Xchuang ,

Thanks a lot for the help

Regards,
Karthik