High-Order Sigma Delta (for DAC) or EF Sigma-Delta

The topic is Error-Feedback Sigma Delta, it's a pretty impressive topology but I can't get one working!!!

**broken link removed**

His theory is that if you have an L-th order sigma delta loop, the error feedback configuration is stable when the adder chain is L+1 bits wide.

I find this is not the case. Using any order sigma delta (I tried 2, 3, and 4th order) it is fairly easy to explode the loop. In fact, for many inputs the error feedback configuration is not at all stable - I am wondering if anyone has successfully implemented either a 4th order digital loop or any order error-feedback loop.

My transfer functions are as follows (I will abbreviate z-3 meaning z^-3)
Second order:
H(z) = 2*z-1 - z-2

Third Order:
H(z) = 3*z-1 - 3*z-2 + z-3

Fourth Order:
H(z) = 4*z-1 - 6*z-2 + 4*z-3 - z-4


Pretty strightforward - anyone worked on these topics?

First of all I have not worked on Error-feedback SD DAC, I designed only SD ADC which is another story..

However I read this paper - the ideas seems to be pretty straightforward.

You are using Lth order differentiator for the EF loop. The authors also use the 4th order differentiator in the example #1. For which inputs did you get the unstable configuration??

Another question is - how did you simulate it (Shreier's package for Matlab or smth else?).

Write more about your simulations - maybe I'll be able to give you some suggestions..

Hi,
I am also designing a 2nd order EF structure by VHDL. I've Read Mr. Peter's theory and I agree with you. I'm not sure yet. The structure adders show overflows but I don't have any idea about stability. I'm in doubt for my correct design.