JacquesKleynhans
Member level 2
Hi Guys I have been developing code for better part of the last couple of months as well I only learned VHDL in the last couple of months to connect a omnivision 0v5620 to fpga controlled by a pic (for the sccb of the camera) and connected to sram.
I have basically tried everything but my code does not work or at least not work correctly. Please Please can some one help me.....
Please guys I know Its a lot of code, but can some please check it out please. Think the issue might be in the data flow section.
Here it goes
Top file responsible for counting incoming rows to crop image size , set control lines to sram and include all components.
This Component is responsible for tri stating my input and output for flow controll to and from the sram I think this might be the culprit but not sure.
The last three components are responsible for generating the read address and
write address and also select witch address is send to the output of the sram.
Please guys I know Its a lot of code, but can some please check it out please
Kindest Regards
JAcques
I have basically tried everything but my code does not work or at least not work correctly. Please Please can some one help me.....
Please guys I know Its a lot of code, but can some please check it out please. Think the issue might be in the data flow section.
Here it goes
Top file responsible for counting incoming rows to crop image size , set control lines to sram and include all components.
Code:
-- camera_payload.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity camera_payload is
port (
main_clk : in std_logic;
main_reset : in std_logic;
-- DATA FROM CAMERA TO SRAM
cam_data : in std_logic_vector (7 downto 0); -- data from camera
memory_inout : inout std_logic_vector (7 downto 0); -- data to and from ram
data_out : out std_logic_vector (7 downto 0); -- data to pic
--GENERAL CONTROL LOGIC
enable : in std_logic; -- enable operation bit
read_write : in std_logic; -- read\not write
ack : out std_logic; -- acknowledge bit
read_clk : in std_logic; -- enables read clk
--SRAM
--ADDRESS
address_out : out std_logic_vector (21 downto 0); -- adress of ram
--LOGIC SIGNALS
sram_we : out std_logic;
sram_oe : out std_logic;
sram_cs1 : out std_logic;
sram_cs2 : out std_logic;
sram_byte : out std_logic;
sram_lb : out std_logic;
sram_ub : out std_logic;
--CAMERA
cam_href : in std_logic -- href from camera
- cam_pclk : in std_logic; -- pclk from camera
-- cam_vsync : in std_logic; -- vsync from camera
cam_xvclk : out std_logic -- xvclk to camera
);
end camera_payload;
architecture behavior of camera_payload is
-- attribute syn_preserve : boolean;
-- attribute syn_preserve of behavior: architecture is true;
signal write_adr : std_logic_vector(21 downto 0);
signal read_adr : std_logic_vector(21 downto 0);
signal pll_lock : std_logic;
signal global_reset : std_logic;
signal state_enable : std_logic;
signal count_rows : std_logic_vector (10 DOWNTO 0) := "11111111111";
signal cam_data : std_logic_vector(7 downto 0);
signal pixel_clk : std_logic;
signal write_count :std_logic_vector(7 downto 0) := "00000000";
component dataflow_control is
port
( state_enable : in std_logic;
output_enable : in std_logic;
camera_clk : in std_logic;
readclk : in std_logic;--***************************************
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
data_inout : inout std_logic_vector(7 downto 0)
);
end component ;
component adress_select is
port ( write_adr : in std_logic_vector (21 downto 0); -- write address gen
read_adr : in std_logic_vector (21 downto 0); -- read address gen
-- enable : in std_logic; -- enable module
read_write : in std_logic; -- write or read
sram_adr_out : out std_logic_vector (21 downto 0) -- address to sram
);
end component;
component address_write is
port ( main_reset : in std_logic; -- main reset
enable : in std_logic; -- enable module
cam_pclk : in std_logic; -- pixel clock
cam_href : in std_logic; -- new line acknowledge
read_write : in std_logic; -- read \ not write
write_adr : out std_logic_vector (21 downto 0));-- adress to RAM
end component;
component address_read is
port ( main_reset : in std_logic; -- main reset
enable : in std_logic; -- enable module
read_clk : in std_logic; -- pic clock
read_write : in std_logic; -- read \ not write
read_adr : out std_logic_vector (21 downto 0));-- adress to RAM
end component;
component payload_pll is
port(powerdown : in std_logic;
clka : in std_logic;
lock, gla : out std_logic);
end component;
BEGIN
stage0: dataflow_control port map (state_enable,read_write,pixel_clk,read_clk,cam_data,data_out,memory_inout);
stage1: address_write port map (main_reset,enable,pixel_clk,cam_href,read_write,write_adr);
stage2: address_read port map (main_reset,enable,read_clk,read_write,read_adr);
stage3: adress_select port map (write_adr,read_adr,read_write,address_out); --removed ,state_enable
stagepll: payload_pll port map( '1', main_clk, pll_lock, pixel_clk);
process (pll_lock,main_reset)
begin
global_reset <= pll_lock and main_reset;
end process;
-- THIS PROCESS I USE FOR TESTING INPUT
process(pixel_clk, global_reset, enable)
begin
if (global_reset = '1') then
write_count <= "00000000";
elsif rising_edge(pixel_clk) then
if enable = '1' then
write_count <= std_logic_vector(unsigned(write_count) + 1);
else
write_count <= "00000000";
end if;
end if;
end process;
cam_data <= write_count;
process(cam_href,read_write,enable,main_reset)
begin
if main_reset = '1' then
count_rows <= "11111111111";
ack <= '0';
elsif rising_edge (cam_href) then
if read_write = '0' and enable = '1' then
count_rows <= std_logic_vector(unsigned(count_rows) + 1);
if count_rows = "11000000000" then
count_rows <= "11111111111";
ack <= '1';
end if;
end if;
end if;
end process;
process (enable,read_write)
begin
if (enable = '1') then
state_enable <= '1';
if (read_write ='0') then
sram_oe <= '0';
sram_we <= '0';
sram_cs1 <= '0';
sram_cs2 <= '1';
sram_byte <= '0';
sram_lb <= '0';
sram_ub <= '0';
elsif (read_write = '1') then
sram_oe <= '0';
sram_we <= '1';
sram_cs1 <= '0';
sram_cs2 <= '1';
sram_byte <= '0';
sram_lb <= '0';
sram_ub <= '0';
end if;
else
state_enable <= '0';
sram_oe <= '1';
sram_we <= '1';
sram_cs1 <= '0';
sram_cs2 <= '1';
sram_byte <= '0';
sram_lb <= '0';
sram_ub <= '0';
end if;
end process;
END behavior;This Component is responsible for tri stating my input and output for flow controll to and from the sram I think this might be the culprit but not sure.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dataflow_control is
port
(
state_enable : in std_logic;
output_enable : in std_logic;
camera_clk : in std_logic;
readclk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_inout : inout std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end dataflow_control;
architecture behavior of dataflow_control is
signal data_in_reg :std_logic_vector(7 downto 0);
signal data_out_reg :std_logic_vector(7 downto 0);
begin
process(camera_clk,state_enable,data_in)
begin
if (state_enable = '1' and rising_edge(camera_clk)) then
data_in_reg <= data_in;
end if;
end process;
process(readclk,state_enable,data_out_reg)
begin
if (state_enable = '1' and rising_edge(readclk)) then
data_out <= data_out_reg;
end if;
end process;
process(output_enable,data_inout,data_in_reg)
begin
if output_enable = '1' then
data_inout <= "ZZZZZZZZ";
data_out_reg <= data_inout;
else
data_inout <= data_in_reg;
data_out_reg <= data_inout;
end if;
end process;
end behavior;The last three components are responsible for generating the read address and
write address and also select witch address is send to the output of the sram.
Code:
-- address_read.vhdlibrary ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity address_read is
port ( main_reset : in std_logic; --main reset
enable : in std_logic; -- enable module
read_clk : in std_logic; -- pic clock
read_write : in std_logic; -- read \ not write
read_adr : out std_logic_vector (21 downto 0)); -- adress to RAM
end address_read;
architecture behavior of address_read is
signal adr_cntr_read : std_logic_vector (21 downto 0) := "0000000000000000000000";
begin
process (main_reset, read_write,enable,read_clk)
begin
if main_reset = '1' then
adr_cntr_read <= "0000000000000000000000";
elsif rising_edge(read_clk) then
if enable = '1' and read_write = '1' then
adr_cntr_read <= std_logic_vector(unsigned(adr_cntr_read) + 1);
else
adr_cntr_read <= "0000000000000000000000";
end if;
end if;
end process;
--OUTPUT ASSIGNMENTS
read_adr <= adr_cntr_read;
end behavior;
Code:
-- address_write.vhd
--address will; be generated on the rising edge of cam_pclk when cam_href is 1, write is selected and module enabled
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity address_write is
port ( main_reset : in std_logic; -- main reset
enable : in std_logic; -- enable module
cam_pclk : in std_logic; -- pixel clock
cam_href : in std_logic; -- new line acknowledge
read_write : in std_logic; -- read \ not write
write_adr : out std_logic_vector (21 downto 0));-- adress to RAM -- main reset
end address_write;
architecture behavior of address_write is
signal adr_cntr_write : std_logic_vector (21 downto 0) := "0000000000000000000000";
begin
process (main_reset,enable,cam_href,read_write,cam_pclk)
begin
if main_reset = '1' then
adr_cntr_write <= "0000000000000000000000";
elsif rising_edge(cam_pclk) then
if cam_href = '1' and enable = '1' and read_write = '0' then
if enable = '0' then
adr_cntr_write <= "0000000000000000000000";
else
adr_cntr_write <= std_logic_vector(unsigned(adr_cntr_write) + 1);
end if;
end if;
end if;
end process;
-- OUTPUTS ASSIGNMENTS
write_adr <= adr_cntr_write;
end behavior;
Code:
-- adress_select.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adress_select is
port ( write_adr : in std_logic_vector (21 downto 0); -- write address gen
read_adr : in std_logic_vector (21 downto 0); -- read address gen
-- enable : in std_logic; -- enable module
read_write : in std_logic; -- write or read
sram_adr_out : out std_logic_vector (21 downto 0) -- address to sram
); -- adress send to RAM
end adress_select;
architecture behavior of adress_select is
begin
sram_adr_out <= write_adr when (read_write = '0') else read_adr when (read_write = '1');
end behavior;Please guys I know Its a lot of code, but can some please check it out please
Kindest Regards
JAcques
